Rev 1.0 | SC5507A & SC5508A
Hardware Manual
SignalCore, Inc.
38
SC5507A & SC5508A Hardware Manual
6
0x03
0x0D
7
0x02
0x07
Writing to the Device
Bytes that are written to the device must go through the bridge chip. In this section, we will first look at
the write cycle of each byte, and then the write cycle of each device register. Do note the difference
between the bridge register addresses and the device register addresses.
Single Byte Write
The serial transfer buffer register address is located at 0x00 offset from BAR0 of the bridge chip, however,
before writing byte data to this register, its status needs to be checked to confirm that it is ready to
accept a new buffer of bytes. The status register is located at 0x05, and it must be read and bit 7 must be
high to indicate that the transfer register is ready to receive the next byte buffer. Checking the status
register of the serial bridge chip is required before every new command write.
Device Register Write
The process of writing the device registers is the same as writing a RS232 port, so the description of
Section 5.4.1 is applicable. Writing the device registers involves sending byte-by-byte data as described
previously. Section 4.1 provides information on the number of configuration write bytes needed for each
device register. The first byte sent is the device register address, followed by the most significant byte of
the register’s associated data. When a device register is fully w
ritten, that is, all its data has been sent to
the device, it will return 1 byte. This returned byte must be read (by the host) to clear the transfer buffer
so that later received data are not corrupted. Section 5.5.3.1 describes how a byte read cycle is
performed.
Reading from the Device
Device data is passed back to the host via the bridge chip byte-by-byte, so we will discuss a single byte
read process and an entire register read process.
Single Byte Read
The serial transfer buffer register address is located at 0x00 offset from BAR0 of the bridge chip. Before
valid data can be read from the transfer register, its ready status must first be confirmed. The status
register is located at 0x05, and it must be read and bit 0 must be high to indicate that valid data is
available. Checking the status register for available data is required before every byte read.
Device Register Read
After a
write request
to the device is made, 8 bytes of data is available to be read back. Use the single
byte read process, as mentioned previously, to read all the bytes. See Section 4.2 for information of the
exact number of request write bytes, and the number of request read bytes, which is 8. All 8 bytes must
be read to fully clear the transfer buffer. The first byte read is the most significant byte.
