EAN-4000-OEM-MIPI-Cameras
© SightLine Applications, Inc.
12
A3 Connector Requirements
•
Four data lanes.
•
One clock lane.
•
Reset and standby for camera
control in Linux driver.
•
I2C lines for setting register in the
camera, used by the Linux driver.
Figure A1: MIPI Connector Pinout
Appendix B - MIPI Camera Capture Requirements - Custom MIPI Inputs
This section covers requirements for customers that externally convert camera data into MIPI signals
input to the 4000-OEM. The system consists of a camera, an acquisition system, and an FPGA that can
generate MIPI signals.
The
contains details on implementing a design with external FPGAs to interface with
the 4000-OEM. See the
Customer Designed 4000-OEM Boards and Camera Interface Options
section in
the ICD.
The MIPI camera interface consists of a clock signal and 1, 2 or 4 data lanes. The number of data lanes
depends on the camera frame rate and resolution. The MIPI standard also provides for an I2C bus for
camera configuration that may not be used in customer FPGA implementations.
IMPORTANT:
When designing a custom MIPI (FPGA) camera board, it is important to include a way
to externally reset the FPGA and camera state machine. The commercial MIPI cameras that
SightLine supports utilize the I2C bus (over MIPI) and a Linux driver that allows for a camera reset
at appropriate times. An example would be to design an external connection to a 4000-OEM GPIO
pin or to design in an I2C to GPIO/serial bridge chip similar to the design on the
board.
MIPI was designed to support cell phone cameras, which are color cameras in 8, 10, and 12 bits. There
is no support in the packet types for 14-bit IR grayscale cameras or 16-bit YCbCr cameras.
