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Understanding Module Operation
3-11
High Speed Counter Encoder Module User Manual
The following options can only be selected with bit WY20.01 cleared, which
puts the module in Run Mode.
While the inhibit bit is set, it inhibits (pauses) the counting of Counter 1
and bit WY19.05 inhibits the counting of Counter 4.
When set, Reset Counter 1 (WY19.02) and Counter 4 (WY19.06) clears the
count value to 0. The reset bit provides the Reset-and-Go function.
When set, Reset 16-bit Counters 2 and 3 (WY19.03 and WY19.04) and 16-bit
Counters 5 and 6 (WY19.07 and WY19.08) functions as a trigger or gate to
the counter.
Table 3-9 shows that setting a bit from WY19.09 through WY19.16 forces
the corresponding output on.
Set the PROGRAM mode flag to place the module in Program Mode. After
programming the module with the required presets and programming
values, clear the Program Mode flag to place the module in RUN Mode. If no
fault is found by the module, bit WX18.01 (module in RUN Mode) is set.
The update preset values bit reloads all the counters with their preset
values. When all counters have been, loaded WX18.02 is set. For Counters 1
and 4, the current count values are not affected. The compare function uses
the new preset values. For the divide-by-N mode, the preset is loaded and
the counting resumes from the new preset value at the next rollover. For
Counters 2, 3, 5 and 6, the count values are loaded with the new preset
values, and counting starts on the next clock edges from the preset value.
Set the latch holding registers bit to halt the INDEX or Period signals from
updating the values in the Holding Registers.
Set the disable outputs bit to disable all outputs, turning them off.
Set the enable interrupt mode bit to enable the Interrupt function. Outputs
that have been enabled in bits WY19.09 through WY19.16 can now cause an
interrupt request to be generated. Bit WX18.06 is set to indicate that an
interrupt request is active.
Set the clear interrupt bit to clear an interrupt request. Once an interrupt
request has been generated, additional changing outputs are OR’ed into
WX18.09 through WX18.16. Setting this flag clears bit WX18.06, and bits
WX18.09 through WX18.16 resume as output status indicators.
Set bit WY20.07 to clear Output 1 latch, set by preset 1 (Counter 1).
Set bit WY20.08 to clear Output 5 latch, set by preset 5 (Counter 4).
Inhibit Bits: WY19.01
and WY19.05
Reset Bits: WY19.02
and WY19.06
Reset Bits:
WY19.03, 04 and
WY19.07, 08
Force Output Bits:
WY19.09 through
WY19.16
Program Mode
Flag Bit: WY20.01
Update Preset
Values Bit: WY20.02
Latch Holding
Registers Bit:
WY20.03
Disable Outputs Bit:
WY20.04
Enable Interrupt
Mode Bit: WY20.05
Clear Interrupt Bit:
WY20.06
Clear Output
Latches Bits:
WY20.07 and
WY20.08