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PROFIBUS Controller SPC 4®-2 LF 

52 

C79000-G8976-C157-3

 

6.1 Description 

Supported Productive Services 

The SPC 4-2 supports the following productive services of PROFIBUS DP (DIN 
19245 part 3, EN 50170 volume 2, IEC 61158, IEC 61784-1) 

 

●

 Data 

Exchange 

●

  Read Input Data 

●

 Read 

Output 

Data 

●

  Global-Control (Sync, Freeze, Clear-Data) 

Other DP Services 

Other PROFIBUS-DP services (diagnostics, parameter assignment, and 
configuration) must be implemented by the FLC; in other words, the software must 
operate the appropriate SAPs according to the PROFIBUS DP state machine.  

If the SPC 4-2 is to support the services above, DP mode = 1 must be set in mode 
register 0. 

In the DP mode, the data exchange between the DEFAULT SAP of the DP master 
and the DEFAULT SAP of the DP slave is achieved using swap buffers: 

The indication buffers D, N, and U are available for received data (output data). 
The reply update buffers D, N, and U are used for reply data (input data). 

Interrupt 

An indication interrupt is not generated. If new output data are available to the FLC, 
the "Output Data Exchange" interrupt is generated. The "Watchdog Reset" interrupt 
shows that valid output data have been received from the DP master at the 
DEFAULT SAP. The "Watchdog Reset" interrupt, instructs the FLC to reset the 
"Software Watchdog" that monitors the activity of the DP master. 

Summary of Contents for SIMATIC NET SPC 4-2 LF

Page 1: ...iew 2 Pin Assignment 3 Memory Assignment 4 FLC Interface 5 DP Interface 6 ASIC Interface 7 Asynchronous Interface 8 Synchronous Interface 9 Clock Pulses 10 Processor Interface 11 Technical Specifications 12 Package 13 References 14 Addresses 15 Appendix 16 C79000 G8976 C157 3 Release 12 2006 ...

Page 2: ...our own personal safety as well as to protect the product and connected equipment These notices are highlighted in the manual by a warning triangle and are marked as follows according to the level of danger Danger indicates that death severe personal injury will result if proper precautions are not taken Warning indicates that death severe personal injury can result if proper precautions are not t...

Page 3: ... equipment and systems in accordance with established safety practices and standards Correct Usage of Hardware Products Note the following Caution This product may only be used for the applications described in the catalog or the technical description and only in connection with devices or components from other manufacturers which have been approved or recommended by Siemens This product can only ...

Page 4: ...om other manufacturers which have been approved or recommended by Siemens Before you use the supplied sample programs or programs you have written yourself make certain that no injury to persons nor damage to equipment can result in your plant or process Prior to Commissioning Prior to commissioning note the following warning Caution Prior to startup read the relevant documentation For ordering da...

Page 5: ...ontrol Byte 37 5 1 3 Request SA 38 5 1 4 Request SSAP 38 5 1 5 Access Byte 38 5 1 6 Reply Update Ptr SDN DDB Tln Tab Ptr 40 5 1 7 Special Features of the DEFAULT SAP 41 5 2 SM SAP List 43 5 3 Indication Queue 44 5 3 1 Description 44 5 3 2 Structure of the Indication Block 46 5 4 Reply on Indication Blocks 47 5 4 1 Description 47 5 4 2 Structure of the Reply on Indication Blocks 48 6 DP Interface 5...

Page 6: ...rrupt with 16 Byte Segments 88 7 7 FF Mode 89 7 7 1 Send and Receive Buffer Structure 89 7 7 2 Sending 89 7 7 3 Receiving 89 7 8 Error Trigger Signal 91 7 9 Interrupt Controller 93 7 9 1 Interrupt Assignment 94 7 9 2 Interrupt Assignment in the FF Mode 96 7 10 Clock Synchronization 98 7 11 SPC 4 2 Timers 100 7 11 1 Delay Timer 100 7 11 2 Idle Timer 101 7 11 3 Syni Timer 102 7 11 4 Slot Timer 103 7...

Page 7: ...ing 137 11 6 Reset Timing 138 11 7 Intel Siemens 8051 synchronous etc 139 11 7 1 Circuit Diagram 139 11 7 2 Timing 80C32 140 11 8 Intel X86 asynchronous 142 11 8 1 Circuit Diagram 142 11 8 2 Timing x86 143 11 9 Siemens 80C165 asynchronous 145 11 9 1 Circuit Diagram 145 11 9 2 Timing 80C165 146 11 10 Timing 68HC16 asynchronous 148 11 10 1 Timing 68HC16 148 11 11 Motorola 68HC11 synchronous 150 11 1...

Page 8: ...US Controller SPC 4 2 LF 8 C79000 G8976 C157 3 14 References 167 15 Addresses 169 15 1 PNO 170 15 2 Contacts in the Interface Center 171 16 Appendix 173 16 1 Server Software for the SPC 4 2 174 16 2 SIM1 176 ...

Page 9: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 9 Introduction 1 ...

Page 10: ... additional microprocessor is required In addition to the layer 2 functionality the following productive services are also integrated on the ASIC Data_Exchange Read_Input Read_Output and the Global_Control command of DIN E 19245 Part 3 EN50170 IEC61158 as well as the PROFIBUS PA functionality DIN E 19245 Part 4 EN 50170 IEC 61158 IEC 61784 1 SPC 4 2 supports the following communication profiles PR...

Page 11: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 11 Functional Overview 2 ...

Page 12: ...id timing or asynchronous with Ready support processor bus timing The handshake between the processor and the SPC 4 2 is executed by the FLC firmware Field Bus Link Control synonym for all communication stacks via the dual port RAM extended to 3 Kbytes integrated on the SPC 4 2 From the point of view of the user the SPC 4 2 occupies an address space of 1 Kbyte The plausibility check when request f...

Page 13: ...e SPC 4 2 are activated using previously unused parameter registers The SPC 4 SPC 4 1 does not evaluate address bits 7 to 5 when the parameter registers are accessed so that all registers can be accessed under several addresses write and read All the SPC 4 SPC 4 1 and 4 new SPC 4 2 registers are within this accessible address space By activating the Enable SPC 4 2 bit the SPC 4 2 evaluates all add...

Page 14: ...PROFIBUS Controller SPC 4 2 LF 14 C79000 G8976 C157 3 ...

Page 15: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 15 Pin Assignment 3 ...

Page 16: ...t clock divided by 2 or 4 System CPU 8 Type I Data format of processor interface see Mode Table 9 XINT L Interrupt output CPU Interrupt Contr 10 XINTCI L Port pin in the compatibility mode in the extended mode interrupt output clock synchronization CPU Interrupt Contr Port pin bit 1 of mode register 2 11 DB0 I O Data bus CPU memory C32 mode data address bus multiplexed 12 DB1 I O Data bus CPU memo...

Page 17: ...ADD L Request To Send RS 485 transmitter 28 VSS 29 AB8 I Address bus System CPU C32 mode log 0 30 RXD RXS I Serial receive channel RS 485 receiver 31 AB7 I Address bus System CPU C32 mode log 0 32 AB6 I Address bus System CPU C32 mode log 0 for CS 33 XCTS I Clear to Send log 0 clear to send MODEM FSK 34 XTEST0 I Pin must be connected to VDD 35 XTEST1 I Pin must be connected to VDD 36 RESET I Reset...

Page 18: ...PROFIBUS Controller SPC 4 2 LF 18 C79000 G8976 C157 3 ...

Page 19: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 19 Memory Assignment 4 ...

Page 20: ...ess space Parts of the internal RAM are located directly in the address range of the microprocessor the other parts can be addressed using a window mechanism see Figure 4 1 Micro processor SPC42 0H 0xBFFH 3 kB RAM 0H 1FFH 200H 2FFH 300H 3FFH 512 bytes general parameters SAP list 256 bytes memory window 256 bytes controller parameters Latches Figure 4 1 Addressing the Internal 3 Kbyte RAM ...

Page 21: ...C can address up to 256 bytes using the offset address applied to the address pins of the SPC 4 2 The third address window which is also 256 bytes long 300h to 3FFh is used to address the internal latches required for direct control of the hardware These latches are not integrated in the internal RAM area Address bit A9 Address bit A8 Window Select 0 0 Parameter area physically 00h FFh 0 1 Paramet...

Page 22: ...ytes Indication queue Reply on Indication blocks Swap buffer Node table Ident buffer Byte 0 Byte 7 Segment 0 Segment 1 Segment 2 Segment 3 Segment 4 BEGINN PTR UMBR PTR Figure 4 3 Memory Structure 4 2 2 RAM Parameter Block The first 6 or 8 bytes of the integrated RAM contain the general parameters such as the read and write pointers of the indication queue that do not intervene directly in the con...

Page 23: ...y the FLC 02H IND RD RD WR The read pointer of the indication queue is also a segment address and is managed by the FLC 03H FDL Ident Ptr RD WR Pointer to the Ident buffer 04H TS ADR REG RD WR Contains the node address PROFIBUS PA 0 119 Normal node 120 124 Temporary node for example handheld 125 Default address for temporary nodes 126 Default address for permanent nodes 127 Broadcast multicast PRO...

Page 24: ...e pointer must be used The area of the service access points SAPs occupies 361 bytes address 18H 180H The SAP list is made up of the following 5 SM SAPs System Management Service Access Point each 5 bytes long DEFAULT SAP Service Access Point with 16 bytes 64 SAPs each 5 bytes long Table 5 1 shows the SAP list the functions of the individual registers and bits are explained in the following sectio...

Page 25: ...ocks that have been processed are taken out of the queue The indication queue is organized using write and read pointers The indication read pointer IND RP must be set by the FLC while the hardware of the SPC 4 2 is responsible for updating the indication write pointer IND WP Since this is a ring buffer the end of the queue must be monitored when data are entered If this is exceeded the address mu...

Page 26: ... that the segment size is then 16 bytes instead of 8 bytes New segment address base pointer AB7 3 end pointer begin pointer 8 byte segment in the compatibility mode New segment address base pointer AB7 4 end pointer begin pointer 16 byte segment in the SPC 4 2 mode Along with the 3 or 4 least significant address bits the result forms the physical 11 bit or 12 bit address for the internal RAM With ...

Page 27: ...OFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 27 Base point register Address bus bits 7 0 A11 A4 Byte address within a segment 12 bit RAM address Figure 4 6 Calculating Physical RAM Address in the Extended SPC 4 2 Mode ...

Page 28: ...te registers are accessed via this interface it does not matter whether the SPC 4 2 is in the Intel or in the Motorola mode When the word registers are accessed two byte registers the SPC 4 2 distinguishes between the Intel and Motorola mode Example INT MASK REG Intel mode Write access with address 300 INT MASK REG 7 0 is written little endian Motorola mode Write access with address 300 INT MASK R...

Page 29: ...em Lock 0 Memory lock cell 319H reserved 31AH reserved 31BH reserved 31CH reserved 31DH reserved 31EH reserved 31FH reserved 320H Timer0 Reg 15 8 Timer 0 high byte 15 8 only SPC 4 2 mode 321H Timer0 Reg 7 0 Timer 0 low byte 7 0 only SPC 4 2 mode 322H Timer1 Reg 15 8 Timer 1 high byte 15 8 only SPC 4 2 mode 323H Timer1 Reg 7 0 Timer 1 low byte 7 0 only SPC 4 2 mode 324H Timer2 Reg 15 8 Timer 2 high...

Page 30: ... mode 317H TSYN The following time is set TSYN 33 bit asynchronous mode TIFG interframe GAP time synchronous mode 318H Mem Lock 0 Memory lock cell 319H BEGIN PTR 7 0 The BEGIN PTR points to the lowest segment address of the indication queue The BEGIN PTR must always point to the beginning of an 8 byte segment 31AH Mode Reg2 7 0 Settings for individual bits 31BH Mode Reg3 7 0 Settings for individua...

Page 31: ...orola Name Meaning write access 328H Error Hi Reg 15 8 Writing to this register also deletes Error Hi Reg and Error Lo Reg 329H Error Lo Reg 7 0 Writing to this register also deletes Error Hi Reg and Error Lo Reg Table 4 8 Assignment of the Internal Parameter Registers Only for Write Access ...

Page 32: ...PROFIBUS Controller SPC 4 2 LF 32 C79000 G8976 C157 3 ...

Page 33: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 33 FLC Interface 5 ...

Page 34: ...9000 G8976 C157 3 5 1 SAP List 5 1 1 Structure of the SAP List The SAP list is made up as follows 5 SM SAPs System Management Service Access Point each 5 bytes long DEFAULT SAP Service Access Point with 16 bytes 64 SAPs each 5 bytes long ...

Page 35: ...ply Update Ptr SDN DDB Tln Tab Ptr Pointer to the reply buffer 36H Reply Update Ptr D 37H Reply Update Ptr N 38H Reply Update Ptr U 39H Response Buffer Length 3AH Response Status 3BH Indication Buffer Ptr D 3CH Indication Buffer Ptr N 3DH Indication Buffer Ptr U 3EH Indication Buffer Length 3FH Active Group Ident 40H Control Command 41H SAP 0 Control byte Bit information 42H Request SA Request sou...

Page 36: ...nication between a DEFAULT SAP and a SAP is possible The SPC 4 2 performs a validation of the request SSAPs Each service access point including the DEFAULT SAP has special entries in the SAP list with which the FLC provides receive resources If the SPC 4 2 receives a frame a non existent SAP it replies with no service activated SD1 response Individual registers are assigned to each SAP in the SAP ...

Page 37: ...icated Bit 4 RS RA or UE No service activated Service access point blocked or user error the SPC 4 2 sets this flag when the validation of the request SA was negative request SA does not match received SA in other words the call comes from an unauthorized node The SPC 4 2 replies with Service Access Point Blocked RA in the PA mode or no service activated RS in the PROFIBUS mode SD1 response This f...

Page 38: ...y If they do not match the SPC 4 2 sets the event flag no service activated RS in the PA mode and service access point blocked RA in the PROFIBUS mode and replies with no service activated SD1 response If request SA is 00H 7EH request SSAP FFh selects the DEFAULT SAP If the extension bit in the request SA is set and request SSAP FFH SSAP is not validated 5 1 5 Access Byte Description The access by...

Page 39: ... output data in indication buffer N can be adopted 1 The output data in indication buffer N must be replaced by the corresponding clear coding The last received output data are entered in indication buffer N Bit 7 IND U Cleared only with DEFAULT SAP The IND U Cleared bit must be set by the user on entering the fail safe status and reset when the fail safe status is exited The SPC 4 2 does not modi...

Page 40: ...or Request SA Request SSAP 1 8 bits First entry in the DDB Tln list meaning as for Request SSAP Request SA n 8 bits nth entry in the DDB Tln list meaning as for Request SA Request SSAP n 8 bits nth entry in the DDB Tln list meaning as for Request SSAP Table 5 4 SDN DDB Tln List SDN Frames All SDN frames except for SM TIME that is always indicated and DDB response frames can be filtered by the SPC ...

Page 41: ... by swapping the D and N buffers The reply update buffers D N or U contain only the net data Response Buffer Length This value specifies the length of the reply update buffers D N and U 0 to 246 bytes Response Status Specifies the priority of the response frames to the DP master 2 values are permitted 08H Response low priority 0AH Response high priority Indication Buffer Ptr D N and U These 8 bit ...

Page 42: ...d bit by bit with the Group Select Byte of a received global control frame GCT The DP slave is addressed when the AND logic operation returns a value other than zero in at least one position If the group select byte of the GCT is zero all DP slaves are addressed Control Command of a GCT The last received control command of a global control frame is entered here by the SPC 4 2 ...

Page 43: ...on Function Code Description SM1 SM_SDN 2 SM SDN frames SM2 SM_SRD_SLOT_DEL 10 SM SRD Slot Del frames SM3 SM_SRD_SLOT_KEEP 11 SM SRD Slot Keep frames SM4 SM_SRD 1 SM SRD frames SM5 SM_Time 0 SM Time frames Table 5 5 SM SAP List Usage The use of the SM SAPs depends on the control octet No SAP extensions are used analogous to the use of the DEFAULT SAP Based on the received frame CO field the SPC 4 ...

Page 44: ...long as there is free memory available When a request frame call is received the SPC 4 2 validates the frame header characters with the values it has set in the SAP list The structure is described Table 5 1 SAP List The indication queue is managed as a ring buffer with read IND RD and write IND WR pointers The SPC 4 2 is responsible for the write pointer and the FLC is responsible for the read poi...

Page 45: ...quest buffer max 246 bytes 00 valid CFH invalid Indication queue Indication block Indication block n 1 Indication block n BEGINN PTR IND RD IND WR Figure 5 6 Structure of the Indication Queue If a frame is received without a SAP extension rem SAP loc SAP the SPC 4 2 enters 0FFh in the relevant cell If a frame is received without a SAP extension rem SAP loc SAP the SPC 4 2 enters 0FFh in the releva...

Page 46: ...h x6h Send Data with Acknowledge low x3h Send Data with Acknowledge high x5h Send and Request Data low xCh Send and Request Data high xDh SM_Time x0h SM_SRD x1h SM_SDN x2h SM_SRD_SLOT_DEL xAh SM_SRD_SLOT_KEEP xBh Send and Request Data with DDB x7h DDB Response low y8h DDB Response high yAh x Frame type 1 meaning bit 6 1 and FCB FCV according to frame entry y Frame type 0 meaning bit 6 0 and statio...

Page 47: ...has been received error free and validated the response has been sent and the next request frame to another node or with toggled FCB FCV bits to the local station address has been correctly received If the SPC 4 2 receives an SRD or DDB request frame with a net data length 0 and if the response data length is also 0 the SPC 4 2 does not enter this frame in the indication queue and does not indicat...

Page 48: ...e 2 Net data resp buf data length resp status 08h 18h lowprior 0Ah 1Ah highprior Buffer of responder resp buf ptr UMBR PTR1 Area of reply on indication blocks Figure 5 8 Structure of the Reply on Indication Block The response buffer is included in the Reply On Indication Blocks area and contains the response buffer length the response status and the net data of the response frame ...

Page 49: ...wing codes are permitted Function Code Response FDL FMA1 2 Data low Send Data okay 000x1000b Response FDL FMA1 2 Data high Send Data okay 000x1010b Bit 4 x Single Update Reply If this bit is also set a reply in the indication reply buffer is sent only once Otherwise the SPC 4 2 sends this buffer again with each call frame Reply buffer contains the reply data Byte 3 data 0 Byte 0 of the net data By...

Page 50: ...PROFIBUS Controller SPC 4 2 LF 50 C79000 G8976 C157 3 ...

Page 51: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 51 DP Interface 6 ...

Page 52: ...e SPC 4 2 is to support the services above DP mode 1 must be set in mode register 0 In the DP mode the data exchange between the DEFAULT SAP of the DP master and the DEFAULT SAP of the DP slave is achieved using swap buffers The indication buffers D N and U are available for received data output data The reply update buffers D N and U are used for reply data input data Interrupt An indication inte...

Page 53: ...Reset interrupt Following this the SPC 4 2 swaps the indication buffers D and N either immediately DIAG SYNC mode 0 or at the next Sync command DIAG SYSNC mode 1 After swapping the indication buffer pointers D and N the SPC 4 2 sets the IND N Valid 1 flag in the default SAP and generates the Output Data Exchange interrupt These actions are executed with the lock active to ensure data consistency I...

Page 54: ...ply update buffer N in other words RUP N Valid 0 in the DEFAULT SAP or the input data in reply update buffer D are frozen DIAG FREEZE mode 1 see Section 6 2 4 or with the new input data if the reply update buffers D and N were swapped prior to sending the response The buffers are swapped if RUP N Valid 1 and DIAG FREEZE mode 0 is set The SPC 4 2 then sets the flag RUP N Valid 0 in the DEFAULT SAP ...

Page 55: ...n DEFAULT SAP when the DP controller is in the Data Exchange state The FLC must therefore set Request SA station address of the DP master in the DEFAULT SAP In all other DP states for example Wait PRM Wait Config the DEFAULT SAP must be deactivated by the FLC with Request SA 7FH A request frame from the DP master at the DEFAULT SAP is then rejected with No Service Activated RS In the DP mode the f...

Page 56: ...rames are entered in the indication queue Following this the IND WP PRE and IND WP pointers are set to the next free segment and the IND PRE and IND interrupts are generated If an SRD low high frame is received from the DP master and there are no input data present in other words response buffer length 0 the SPC 4 2 responds as follows either with SC if 08H is entered in the response status of the...

Page 57: ...eue Buffer available is not decremented in the control byte of SAP 56 If input data are requested with Read Input Data the SPC 4 2 replies as follows either with the old input data of reply update buffer D in other words reply update buffers D and N are not swapped before sending the response This is the situation when no valid input data have been entered in the reply update buffer N in other wor...

Page 58: ...d RS In the Data Exchange DP status the following settings must be made in SAP 57 of the SPC 4 2 Buffer available 0 Request SA 0FFH all Request SSAP SSAP different from DEFAULT SAP Access Value 09H 0AH 0BH Reply Update Ptr SDN DDB Tln Tab Ptr don t care Read Output Data frames are not indicated by the SPC 4 2 and not entered in the indication queue Buffer available is not decremented in the contro...

Page 59: ...tation address of DP master Request SSAP SSAP different from DEFAULT SAP Access Value 01H 02H 03H Reply Update Ptr SDN DDB Tln Tab Ptr don t care Buffer available is not decremented in the control byte of SAP 58 A global control frame with a net data length other than 2 is not evaluated by the SPC 4 2 if Check GCT Length Off 0 is set in mode register 2 If Check GCT Length Off 1 is set monitoring o...

Page 60: ...alid 0 The SPC 4 2 executes these actions with lock active If input data are requested from the SPC 4 2 with a request frame in the freeze mode the SPC 4 2 responds with the old input data of reply update buffer D in other words reply update buffers D and N are not swapped prior to sending the response 4 Unsync If unsync is set the SPC 4 2 deactivates the sync mode DIAG SYNC mode 0 and swaps the i...

Page 61: ... also stored in the DEFAULT SAP 6 2 5 Leave Master Description With Leave Master the SPC 4 2 executes the following actions Output data in indication buffer D are deleted or more precisely written with 00H Following this indication buffers D and N are swapped with lock active The Control Command byte in the default SAP is deleted in other words Control Command FFH The Output Data Exchange interrup...

Page 62: ...auds tLM 20 n 2 bit clocks Notice With Leave Master there is a risk that request frames received at the SPC 4 2 during the execution time tLM are lost Since the receiver of the SPC 4 2 is operational during the time tLM but cannot be processed a FIFO Overflow interrupt is possible 6 2 6 Baudrate Search Description If the Baudrate Search bit is set in mode register 1 the automatic baud rate search ...

Page 63: ...ASIC Interface PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 63 ASIC Interface 7 ...

Page 64: ...atch array on the SPC 4 2 All other parameters are in the lower area of the RAM The FLC transfers operating data to the SPC 4 2 in the parameter cells Parameters are set only in the offline status for example after turning on All parameters must be loaded before the SPC 4 2 can leave the offline status START SPC 4 2 1 mode register 1 Some control bits must however be modified continuously during o...

Page 65: ... 8 305H Intel TS L1 3 TS L 12 TS L 11 TS L 10 TS L 9 TS L8 TSLOT 13 8 Table 7 1 Slot Time Register The wait to receive time TSL is a maximum of 14 bits long and is specified in transmission bit steps It is required to calculate the timeout 7 1 2 Baudrate Register can be written modifiable only in offline status Address Bit Position Meaning Control register 7 6 5 4 3 2 1 0 306H Intel BR7 BR6 BR5 BR...

Page 66: ...SYN ASYN bits of mode register 0 SYN ASYN FILTER AN AUS ABTAST 0 0 16 0 1 16 1 0 4 1 1 16 The following table lists the dividing factors for the individual baud rates for both modes CLK Baudrate BR Dividing factor G for ABTAST 4 Dividing factor G for ABTAST 16 48 MHz 12 0 MBd 0 48 MHz 6 0 Mbd 1 48 MHz 3 0 Mbd 3 0 48 MHz 1 5 Mbd 7 1 48 MHz 500 00 kbd 23 5 48 MHz 187 50 kbd 63 15 48 MHz 93 75 kbd 12...

Page 67: ...tten modifiable only in offline status Address Bit Position Meaning Control register 7 6 5 4 3 2 1 0 310H UP TR 7 UP TR 6 UP TR 5 UP TR 4 UP TR 3 UP TR 2 UP TR 1 UP TR 0 UMBR PTR Reg 7 0 Table 7 5 UMBR PTR Register The UMBR PTR points to the address of the first segment that no longer belongs to the indication queue 7 1 5 BASE PTR Register can be written Address Bit Position Meaning Control regist...

Page 68: ...the DP mode TRDY can be modified dynamically by the DP master sending the DP slave a parameter assignment frame with the new value of TRDY Since the SPC 4 2 does not evaluate parameter assignment frames this must be handled by the FLC The value for TRDY to be set by the FLC is obtained as follows TRDY for SPC 4 2 TRDY from the parameter assignment frame 2 7 1 7 PREAMBLE Register can be written mod...

Page 69: ...be set here In the synchronous mode the TIFG interframe GAP time is set 4 32 bits 7 1 9 Delay Timer Register can be read Address Bit Position Meaning Control register 7 6 5 4 3 2 1 0 306H Intel TD EL 7 TD EL 6 TD EL 5 TD EL 4 TD EL 3 TD EL 2 TD EL 1 TD EL 0 DELAY 7 0 Address Bit Position Meaning Control register 15 14 13 12 11 10 7 8 307H Intel TD EL 15 TD EL 14 TD EL 13 TD EL 12 TD EL 11 TD EL 10...

Page 70: ...ntrol register 15 14 13 12 11 10 7 8 30BH Intel TF AK 10 TF AK 9 TF AK 8 TSLOT 13 8 Table 7 11 Factor Delay Timer Clock Register The Factor Delay Timer Clock register determines the dividing factor dependent on the input clock pulse for the delay timer refer to the section on SPC 4 2 timers 7 1 11 Mode Register Mode Register 0 Mode REG0 can be written modifiable only in offline status Fixed parame...

Page 71: ...us mode on the serial interface 0 Synchronous mode status following reset 1 Asynchronous mode Bit 3 XRTS ADD XRTS ADD output switchover for different driver activation 0 RTS status following reset 1 ADD Bit 4 XPB PA Layer 2 setting 0 PROFIBUS mode status following reset 1 PA Mode Bit 5 INT POL Polarity of the interrupt outputs 0 The interrupt outputs are low active status following reset 1 The int...

Page 72: ...odified during operation Some control bits must however be modified continuously during operation These are put together in a special register mode register 1 and can be set Mode_Reg_S or cleared Mode_Reg_R independent of each other Different addresses are used for setting and clearing A logical 1 must be written to the bit position to be set or cleared ...

Page 73: ...n the SM Mode State Bit 3 Go Offline Go to the offline state 1 Once the current job is completed the SPC 4 2 changes to the offline state Bit 4 DEL TIM Delay timer 1 The delay timer is stopped SET or reset RESET Bit 5 Baudrate Search Automatic baud rate search 1 Automatic baud rate search is activated If SD4 or a complete SD1 SD2 SD3 frame is received error free the Correct SD interrupt is generat...

Page 74: ...tended by three bits 7 5 in the SPC 4 1 and therefore also in the SPC 4 2 Mode register 2 can only be written Address Bit Position Meaning Control register 7 6 5 4 3 2 1 0 31AH EN DD B MO DE EN CLOC K SYNC SPEC CLEA R MOD E CHECK GCT RESBIT S OFF CHECK GCT LENGTH OFF X86 XINT CI XHOL DTOK EN Mode Reg2 7 0 ...

Page 75: ...ontrol frame 0 The reserved bits in the command byte of a global control frame are monitored 1 No monitoring of the reserved bits in the command byte of a global control frame If at least one of these reserved bits is logical 1 the SPC 4 2 executes a Leave Master Bit 5 SPEC CLEAR MODE In the Spec_Clear_Mode fail safe mode the SPC 4 2 accepts data frames with a net data length of 0 when the PROFIBU...

Page 76: ...000 G8976 C157 3 Mode Register 3 Mode register 3 can only be written Address Bit Position Meaning Control register 7 6 5 4 3 2 1 0 31BH FF Mod e RX D leve l XHOLDTOKEN Mode Seg ment 16 Quic k Sync New Debu g Pulse modulat ion Mode Reg3 7 0 ...

Page 77: ...ctive Bit 3 Segment16 Activates the 16 byte segments for addressing of the 3K RAM of the SPC4 2 0 8 byte segments reset value 1 16 byte segments in other words complete addressing of the 3K RAM is possible Bit 5 4 XHOLDTOKEN Mode Function of the output pin XHOLDTOKEN 00 After reset XHOLDTOKEN function as for SPC4 SPC4 1 see mode register 2 01 Error trigger signal on receive error pulse 10 Error tr...

Page 78: ... FF mode bit is active in mode register 3 Bit 1 Enable Takt Sync Clock synchronization 0 Reset value 1 The SPC 4 2 reacts to global control frames Bit 3 2 Sampling mode Size of the unsharp window for pulse demodulation 00 Unsharp window 2 5µs to 3 0µs as for the SPC 4 1 01 Unsharp window 3 0 µs to 3 5 µs reset value 10 Unsharp window 3 5µs to 4 0µs 11 Unsharp window 4 0µs to 4 5µs Bit 7 Enable SPC...

Page 79: ...6 5 4 3 2 1 0 304H Intel Enable Receiv er MEM LOC K EARLY READ Y IND PRE Stored IND Stored Passi ve Idle SM state OFF LINE Status Reg 7 0 Address Bit Position Meaning Control register 15 14 13 12 11 10 9 8 305H Intel Chip Version Stn Typ Idlemux SYNI XSL OT Status Reg 15 8 0 1 x x 1 0 x x Version number differs depending on setting of bit 7 in mode 4 register 0 1 Operation in SPC4 1 mode 1 0 Opera...

Page 80: ...t the beginning of the next frame no repetition 1 An indication will be generated early directly after error free reception Bit 5 EARLY READY Early ready signal 0 Ready is generated when the data are valid 1 Ready is generated one clock pulse before the data are valid Bit 6 MEM LOCK Bus access locked 0 No MEM LOCK set 1 The processor has set MEM LOCK Bit 7 Enable Receiver Enables the receiver 0 Th...

Page 81: ... SM mode Bit 12 Version 13 Version ID of the SPC 4 2 01 Version ID in the compatibility mode as for SPC4 1 10 Version ID for SPC 4 2 extended mode Rest Not possible Bit 14 Chip 15 Coding 01 This code stands for the SPC 4 1 and SPC 4 2 Rest Not possible Table 7 17 Status Register ...

Page 82: ... output data in indication buffer N must be replaced by the corresponding clear coding The last received output data are entered in indication buffer N Bit 7 IND U Cleared only with DEFAULT SAP The IND U Cleared bit must be set by the user on entering the fail safe status and reset when the fail safe status is exited The SPC 4 2 does not modify this bit The SPC 4 2 does however scan the bit when S...

Page 83: ... not deleted by the SPC 4 2 in other words not overwritten by 00H If the SPC 4 2 receives a Read Output Data frame it checks the IND U Cleared bit If IND U Cleared 1 is set the SPC 4 2 replies with 00H as the output data With the Spec Clear Mode 1 setting the SPC 4 2 does not delete the output data even when it executes Leave Master or when it receives a global control frame with Clear Data 1 To i...

Page 84: ...egrated delay timer causes a Del Tim Overrun interrupt bit 4 of the interrupt register on the SPC 4 2 as was also the case on the SPC 4 This interrupt allows the user to extend the internal delay timer as required To ensure compatibility with SPC 4 the delay timer of the SPC 4 2 is limited to 16 bits in the PA mode XPB PA 1 in other words the Del Tim Overrun interrupt is generated when the 16 bit ...

Page 85: ...s enabled the parameter bit En DDB mode is of no significance in this mode With the SPC4 4 1 and SPC 4 2 the DDB mechanism is restricted to the default SAP No other SAPs can be operated with DDB The default SAP is the only SAP that provides separate resources for the SDN DDB node table and for reply data reply update buffers D N U in the DP mode If DP Mode 0 is set either the node table for filter...

Page 86: ...ddresses write and read This applies to both writing and reading All SPC4 SPC4 1 registers and 4 new SPC 4 2 registers are located in the accessible address space from 0x300 to 0x31F One of these is the new Mode4 register see Section 7 1 11 If the Bit Enable SPC 4 2 is activated here the SPC 4 2 evaluates all address bits This means that genuine access to addresses beyond 0x31F is possible where t...

Page 87: ...6 byte segments SAP List On the SPC4 SPC4 1 as well as on the SPC 4 2 this area begins at address 24 018h The SAP list is therefore not structured segment oriented in other words the bytes of all 64 SAPs follow on one after the other without gaps This structure was selected because this memory area of the internal RAM can be accessed directly without needing to use a base pointer Indication blocks...

Page 88: ... Indication block can waste a further 8 bytes at the end With an indication queue with space for 2 frames and 20 Reply On Indication blocks the maximum possible wastage is 2 16 20 8 192 bytes 7 6 2 Mem Overflow Interrupt with 16 Byte Segments The Mem Overflow interrupt becomes active with 8 byte segments as soon as there is an attempt to access beyond the 2 Kbyte boundary The Mem Overflow interrup...

Page 89: ...rs must begin at a segment boundary although they themselves are byte oriented in other words they never have gaps regardless of the segment size 7 7 2 Sending The user can trigger sending by writing a 1 to the Start FF Send bit in mode register 4 The SPC 4 2 6 then requires 6 bit times before the frame starts on the bus If the Start FF Send bit is activated while reception is still active there i...

Page 90: ...ngth in the length bytes of the receive buffer and activates the frame received error free interrupt if no errors were detected during reception If an error occurred the bad frame received interrupt is activated In this case the user can decide whether this is a CRC error station type 1 or a Manchester error station type 0 based on bit 11 of the status register station type If there was receive bu...

Page 91: ...hile a frame is being received is also checked In the DP mode the same applies to the checksum error signal A FIFO overflow also counts as a receive error Send errors The send pin of the SPC 4 2 is bi directional in other words the SPC 4 2 can check which level is supplied to its TXD_TXS send pin when sending Instead of this level it can also check using the value supplied by the RXD_RXS input pin...

Page 92: ...ted each time the error trigger signal is activated Once the counter reading FFFF is reached the counter stops and must be deleted by the host by writing to the higher or lower byte The data written has no significance writing to the counter always deletes all 16 bits at the same time To ensure that the higher byte always matches the lower byte when reading out the error counter via the 8 bit data...

Page 93: ...ommon network When debugging the user can set every event in the IRR Every interrupt event processed by the processor must be deleted using the IAR by writing logical 1 to the corresponding bit position If there is a new event and acknowledge pending in the IRR at the same time the event remains stored If the processor then enables a mask make sure that there is no entry from the past in the IRR T...

Page 94: ...tel Correct SD Output Data Exchan ge Wrong SD Watch Dog Reset Syni Error Del Tim Overru n Go Pas sive Idle Go SM State Rec Frame Overflo w MAC _ Rese t Int Reg IR 7 0 Address Bit Position Meaning Control register 15 14 13 12 11 10 9 8 303H Intel IND IND PRE FIFO overfl ow Rese rved Leav e Mast er Write Viola tion timeout Mem Overf low Int Reg IR 15 8 ...

Page 95: ...e DP master Bit 7 Correct SD Output Data Exchange Correct SD When baud rate search 1 When no error occurred receiving a frame and baud rate search was active Output Data Exchange When baud rate search 0 and DP mode 1 Indication buffers D and N were swapped DP data frame without output data in other words with net data length 0 was received Bit 8 Mem Overflow Access was attempted to the internal RA...

Page 96: ... 10 9 8 303H Intel IND Rese rved FIFO overfl ow Rese rved Rese rved Write Viola tion Reserv ed Mem Overf low Int Reg IR 15 8 The other registers of the interrupt controller have the same bit positions as the IR Address register Reset state Assignment 300H 301H Interrupt Request Register IRR Read only 300H 301H Interrupt Mask register IMR can be written can be modified in operation all bits deleted...

Page 97: ...limiter received Bit 8 Mem Overflow Access was attempted to the internal RAM at an address outside the 1 5 Kbytes Bit 9 Reserved Bit 10 Write Violation In total parameter cells in the RAM were overridden externally the SPC 4 2 changes to the offline state Bit 11 Reserved Bit 12 Reserved Bit 13 FIFO overflow FIFO overflow when receiving reception not stopped this should never occur since the SPC 4 ...

Page 98: ...ly internally is switched to the SPC 4 2 output XINTCI without masking and remains active zero active until the software clears the interrupt XINTCI is therefore a new non maskable interrupt output To activate clock synchronization the Enable SPC 4 2 bit must be set in mode register 4 only then is access to the three new registers possible The Enable Takt Sync bit must also be set in mode register...

Page 99: ...use of the digital filter in DP increases the jitter by Tspc4 For PA LE 6 Tdelay min 17 875 Tbit Jitter 2 0 Tbit For PA LE 7 Tdelay min 11 875 Tbit Jitter 1 0 Tbit The use of pulse modulation increases the jitter by Tspc4 As a comparison the values of the DPC31 are shown below see specification DPC31 version 1 0 Tdelay 250 ns Jitter 0 25 Tbit T48 ...

Page 100: ...when a second SM Time frame arrives for example if the first SM Time frame was lost due to a bus problem for further details refer to system management SM Time System management must be capable of handling possible error situations such as two consecutive second SM Time frames from different time masters The FAKT_DEL_CLK divider has a range from 64 to 1536 1 _ _ _ CLK DEL Quarz CLK DEL FAKT Quartz...

Page 101: ...D1 Receive delay timer RD1 start stop RD1 counter is stopped If the maximum counter reading is reached it continues at 0 and an interrupt Del Tim Overrun is triggered y 1 RD1 counter is reset and read out Figure 7 26 Delay Timer Function 2 7 11 2 Idle Timer Description This timer controls the idle phase directly on the internal bus line RxD RxA logical 1 Depending on the frame type the following t...

Page 102: ...nd is incremented with BRCLK The timer is stopped when the idle timer lapses The idle timer therefore controls the syni timer directly If the idle timer is running the syni timer is enabled and vice versa If there is a problem on the transmission medium for example permanent logical 0 or a permanent alternation between 0 1 in the asynchronous mode or permanent activity in the synchronous mode the ...

Page 103: ...r this reason a common syni slot timer 14 bits is used In all MAC states apart from offline the slot timer elapsing causes the timeout timer to increment and the slot timer is loaded with the value 0 and restarted With the next BRCLK it has the value 1 Following initialization the syni slot timer is started as the syni timer START SPC 4 2 1 7 11 5 Timeout Timer Description The Timeout timer is use...

Page 104: ...eout TIMEOUT stop TIMEOUT START TIMEOUT elapsed Figure 7 28 Control of the Timeout Timer 7 11 6 New Timers in the FF Mode Description The SPC 4 2 contains 4 new 16 bit timers These can be used only in the FF mode since they use interrupt bits that are only free in the FF mode They all run at the baud rate speed In the timer type register the user can set the timers either as one shot or as cyclic ...

Page 105: ...ad reached 0 when it stopped To ensure that the higher byte always matches the lower byte when reading out the timer values via the 8 bit data bus the user must always read the lower byte first and then the higher byte while the lower byte is being read the higher byte is copied to register and it is then read from this register Word access to this register is therefore not permitted Note Between ...

Page 106: ...stopped Bit 7 6 00 Status of Timer3 remains unchanged 01 Timer3 is restarted at the start value 10 Timer3 resumes count only effective if timer was previously stopped 11 Timer3 is stopped Address of the Counter Register Bit Position Meaning 7 6 5 4 3 2 1 0 0x320H T0_1 5 T0_1 4 T0_1 3 T0_1 2 T0_1 1 T0_1 0 T0_9 T0_8 Timer0 Reg Bit 15 8 0x321H T0_7 T0_6 T0_5 T0_4 T0_3 T0_2 T0_1 T0_0 Timer0 Reg Bit 7 ...

Page 107: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 107 Asynchronous Interface 8 ...

Page 108: ...ator Description The baud rate generator BRG provides all the clock rates required on the SPC 4 2 for transmitting data in the asynchronous UART format at the following data rates 9 60 Kbps 19 20 Kbps 93 75 Kbps 187 50 Kbps 500 00 Kbps 1 50 Mbps 3 00 Mbps 6 00 Mbps 12 00 Mbps ...

Page 109: ...ure into a serial data stream with a start bit 8 data bits an even parity bit and a stop bit The least significant data bit is sent first Request to Send RTS is generated before the first character The XCTS input is available for connecting a modem Following RTS active the transmitter must hold back the first frame character until the modem activates XCTS ...

Page 110: ...ther bits are scanned three times at the bit mid point at data rates 1 5 Mbps The value for the start bit must be logical 0 and for the stop bit logical 1 With the data bits and the parity bit the receiver makes a two out of the three majority decision If the receiver detects three zeros at the bit mid point when scanning the start bit it aborts synchronization The stop bit with 3 x logical 1 comp...

Page 111: ...Pinout If the interface is to be designed as a standard compliant PROFIBUS interface with a 9 pin sub D female connector keep to the following pin assignment Pin 1 free Pin 2 free Pin 3 B line Pin 4 Request to send RTS Pin 5 Data ground M5 Pin 6 Power supply plus 5V floating P5 current depending on connected device min 10 mA Pin 7 free Pin 8 A line Pin 9 free The cable shield must be connected to ...

Page 112: ...ets the RTS signal to 1 and then loads the transmit buffer of the UART with the first character The UART delays the first character of the frame until the XCTS signal is active During transmission CTS is no longer queried On completion of transmission buffer empty stop bit is sent RTS is reset The XCTS must be set to log 0 during operation Switching times No Symbol Parameters min Unit 1 TsRTS TXD ...

Page 113: ...IN U U U HCPL7101 U U U 68n 68n EN 2M P5 P5 680R 1K OUT EN 680R 300R 680R HCPL0601 2P5 2 74HC132 300R U IN 300R 68n 68n 680R OUT EN U U 20K M M HCPL7101 2P5 2M 300R M CTS RT S TXD RXD B Ltg RTS2M 2P5 A Ltg Caution Potential isolation to bus P5 and 2 P5 Shield Driver selection Diff voltage 2V 1 2 3 4 5 6 7 8 9 Layout Keep lines as short as possible M Figure 8 3 Circuit Diagram ...

Page 114: ...PROFIBUS Controller SPC 4 2 LF 114 C79000 G8976 C157 3 ...

Page 115: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 115 Synchronous Interface 9 ...

Page 116: ...tives defined optionally in the IEC 61158 2 standard is also implemented What is not implemented is the so called Medium Access Unit MAU that includes the transmit pulse shaper the line driver the receive amplifier the receive filter and the line attachment if necessary with remote powering The MAU ASIC SIM1 simplifies the structure of this synchronous interface significantly refer to the appendix...

Page 117: ...Synchronous Interface PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 117 9 2 Baud Rate Generator Description The baud rate generator can generate the data rate 31 25 Kbps ...

Page 118: ... preamble The length of the preamble is stored in the PREAMBLE register The most significant data bit in contrast to the asynchronous interface is set first 5 The transmitter generates a 16 bit CRC field and appends it to the data field PREAMBLE SD FC DA SA Data FCS CRC ED 1 8 bytes 1 byte 1 249 bytes 2 bytes 1 byte Figure 9 2 Frame Structure of the Serial Interface Binary 0 Binary 1 NON DATA NON ...

Page 119: ...asy to implement an adder circuit to control a current control unit as is used in the interface of an intrinsically safe bus node The combination RxS TxS is an advantage when controlling a transformer The RTS and ADD signals are applied to a common output RTS ADD The switchover between two modes can be set with parameters in mode register 0 To guarantee the minimum gap between two frames the trans...

Page 120: ...PROFIBUS Controller SPC 4 2 LF 120 C79000 G8976 C157 3 1 0 1 0 1 0 1 0 1 N N N 1 0 N 1 RTS TxS ADD Figure 9 5 Output Signals of the Synchronous Transmitter ...

Page 121: ...he Manchester decoder obtains the data from the filtered received signal The clock recovery function obtains the CLK1 clock from the filtered received signal The data decoder scans the filtered received signal at the recovered received clock rate RxC positive edge and passes on the scanned value weighted with the polarity information transferred by the decoder state machine POL 1 or POL 0 as the r...

Page 122: ...rame to a series of short pulses It therefore appears at the SPC 4 2 in the following form Each rising edge in the frame produces a high pulse with a width of 5µs each falling edge a high pulse with a width of 2µs between pulses the signal is level 0 The original frame is recovered in the receive unit When a frame is sent by the SPC 4 2 this pulse train is generated from the frame to be sent The o...

Page 123: ...tally so that the SIM1 recognizes pulses shorter than 3 0 µs and longer than 3 5 µs accurately Pulse widths between these limits are detected at random as short or long pulses On the SPC 4 2 the window in which the pulse width is unreliably detected can be shifted Uncertainty window SPC 4 2 2 5 µs to 3 0 µs scan mode 00 3 0 µs to 3 5 µs scan mode 01 following reset 3 5 µs to 4 0 µs scan mode 10 4 ...

Page 124: ...he duration of the last high and low phase before the fourth edge From the average of the these two numbers it calculates a correction value that is taken into account when identifying the midpoint of the bit With this modification the SPC 4 2 can handle more system distortion all rising or falling edges are delayed by the same amount than the SPC4 To activate this improved synchronization mode th...

Page 125: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 125 Clock Pulses 10 ...

Page 126: ...MHz 5 V synchronous 40 MHz 3 3 V asynchronous 20 MHz 3 3 V synchronous 16 MHz Clock timing Distortion of clock signal up to a ratio of TCLL 40 60 permitted At a threshold of 1 5 or 3 7V and 0 7 or 1 8V CLK 2 1 TCLH TCLL Figure 10 1 Clock Timing Quartz connection M P5 2 4 1 300R G U U EN 3 48MHz CLK 5 SPC4 ISCLK Out C 7 Figure 10 2 Quartz Connection ...

Page 127: ...le the processor via a selectable divider Pin 3 0 4 1 2 divided clock rate With the HC11 Motorola family the E clock must only be of the input clock rate of the SPC 4 2 Osc MotorolaCPU INTELCPU E clock 2 internal 4 internal CLK CLK ISCLK Out 2 2 2MHz 48MHz 2MHz 48MHz 500kHz 12MHz 1MHz 24MHz SynchronousbusclockbetweenCPUandSPC 2MHz 48MHz Divider Divider BIU BIU RAM RAM Figure 10 3 Overview of the C...

Page 128: ...PROFIBUS Controller SPC 4 2 LF 128 C79000 G8976 C157 3 ...

Page 129: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 129 Processor Interface 11 ...

Page 130: ...plemented Since the data formats of Intel and Motorola processors are not compatible the SPC 4 2 automatically performs byte swapping when access is in words only when writing or reading a 16 bit register in the parameter area all other parameters must be accessed byte oriented This allows a Motorola processor to read the 16 bit value correctly As usual reading or writing requires two accesses 8 b...

Page 131: ...characteristics Asynchronous bus timing with evaluation of the READY signal 8 bit non multiplexed bus DB 7 0 AB 9 0 The following can be connected HC16 and HC916 types Address decoder on the SPC 4 2 is deactivated CS signal is supplied to the SPC 4 2 The chip select signal exists on all microcontrollers and can be programmed 0 1 synchronous INTEL INTEL CPU Basis 80C51 2 80C32 microcontrollers from...

Page 132: ... with evaluation of the XREADY signal 8 bit non multiplexed bus DB 7 0 AB 9 0 The following can be connected Microcontroller families e g SIEMENS 80C16x and INTEL X86 Address decoder on the SPC 4 2 is deactivated CS signal is supplied to the SPC 4 2 External address decoding is always required External chip select logic if this does not exist on the microcontroller Note Bit X86 in mode register 2 ...

Page 133: ...nterface to the microcontroller It allows the connected microcontroller access to the internal 3 Kbyte dual port RAM Depending on the connected microcontroller types the BIU generates the request signals for the dual port RAM controller from the control signals ALE with internally generated CS signal or E clock rate with an externally applied CS signal ...

Page 134: ... chip select is also activated In the Intel 80C32 configuration mode 0 1 the falling edge of the read write signal to be synchronized is evaluated as a request when the internal CS decoder generates a CS signal at the same time In the Intel X86 configuration mode 0 0 the falling edge of the read write signal to be synchronized is differentiated and in this case the CS signal is evaluated In the 80...

Page 135: ...s to access with LOCK activated at this point in time the dual port RAM controller DPC stops the MS As a result if the FLC reads logical 0 when accessing the mem lock cell the next accesses are made with the lock activated until the flag is reset If the mem lock cell returns a logical 1 the MS is currently accessing the RAM with LOCK activated In this case the FLC must poll the mem lock cell until...

Page 136: ...is provided In conjunction with various other pins this input allows the manufacturer to test the chip via a test bus The interrupted memory RAM and ROM can also be tested During operation the test inputs must be connected to VDD 11 4 2 XHOLDTOKEN Description This pin is not used in the compatibility mode but can be controlled with mode register 2 bit 0 In the extended SPC 4 2 mode an error trigge...

Page 137: ...US Controller SPC 4 2 LF C79000 G8976 C157 3 137 11 5 Interrupt Timing Interrupts No Parameters MIN MAX Unit 1 Interrupt inactive time 48 periods of the SPC 4 2 clock at 48 MHz 1 µs 1 µs 1µs XINT EOI Figure 11 1 Interrupt Timing ...

Page 138: ... Controller SPC 4 2 LF 138 C79000 G8976 C157 3 11 6 Reset Timing Description To allow the SPC 4 2 to be reset correctly it requires a pulse of at least 100 ns duration Reset Min 100 ns Figure 11 2 Reset Timing ...

Page 139: ... bus timing without evaluation of the READY signal 8 bit multiplexed bus ADB 7 0 The following can be connected Microcontroller families e g INTEL SIEMENS PHILIPS Address decoder on the SPC 4 2 is activated CS signal is supplied internally The lower address bits A 7 0 are stored in an internal address latch with the ALE signal On the SPC 4 2 the internal CS decoder is activated and generates its o...

Page 140: ...F 140 C79000 G8976 C157 3 11 7 2 Timing 80C32 In this mode all accesses are started by the falling edge at XRD or XWR AB Read XRD DB Write XWR DB Data valid t9 t10 t12 DB ALE t1 t2 t3 t5 t4 t6 t7 t8 t11 t13 Figure 11 4 Timing 80C32 ...

Page 141: ... AB before XRD 20 30 ns t6 XRD until DB low resistance 18 27 ns t7 Access time of XRD until DB valid T SPC 4 2 52 77 ns t8 XRD until DB high resistance 18 27 ns t9 XWR pulse width 10 ns t10 Hold time AB compared with XWR 0 ns t11 AB to XWR 20 30 ns t12 Setup time DB before XWR 10 15 ns t13 Hold time DB after XWR 5 8 ns Table 11 5 Bus Interface Timing Intel Synchronous Times in brackets apply for 3...

Page 142: ...sponding byte position of the 16 bit data bus when data are read or the lower address bit is not connected and the 80286 accesses words and only the lower byte is evaluated as shown in the diagram WR RD INTR READY Clock generator 48 MHz 80286 Buscontr 82288 82244 DB AB CLK XWR XRD X INT XREADY 80286 system X86 mode 3K 3 Mode TYPE GND SPC4 Reset RTS TxD RxD XCTS 1K GND EPROM 64kB RAM 32kB Address d...

Page 143: ...C 4 2 CS signal is supplied to the SPC 4 2 External address decoding is always required External chip select logic if this does not exist on the microcontroller Note Bit X86 in mode register 2 must be set for this mode 11 8 2 Timing x86 In this mode all accesses are triggered by the falling edge at XRD or XWR The ALE input can adopt any values since it is disabled internally AB X C S R ead X R D D...

Page 144: ...CS XRD until XREADY early 0 TSPC 4 2 18 27 ns t7 XCS XRD until XREADY early normal 0 17 26 ns t8 XCS XRD until XREADY normal TSPC 4 2 2 T SPC 4 2 18 27 ns t9 Pulse width XWR 10 ns t10 Hold time XCS after XWR 0 ns t11 Setup time DB before XWR 10 15 ns t12 Hold time DB after XWR 5 8 ns t13 XWR until XREADY early normal 0 16 24 ns t14 Setup time AB before XWR 20 30 ns Table 11 8 Bus Interface Timing ...

Page 145: ...0 AB 9 0 RD WR 3K 3 GND Port CS Figure 11 9 Circuit Diagram Typ Mode 0 0 asynchronous INTEL INTEL and SIEMENS 16 8 bit microcontroller families Asynchronous bus timing with evaluation of the XREADY signal 8 bit non multiplexed bus DB 7 0 AB 9 0 The following can be connected Microcontroller families e g SIEMENS 80C16x and INTEL X86 Address decoder on the SPC 4 2 is deactivated CS signal is supplie...

Page 146: ...later access is then started by a falling edge at ALE The ALE high phase can shorter than the clock period TSPC 4 2 If the values T4 and T16 for XRD and XWR are not adhered to in this mode access begins only at the falling edge of XWR or XRD and the access times from the table for Intel asynchronous X86 apply ALE AB X C S R ead X R D D B X R EAD Y early X R EAD Y norm al W rite X W R D B t1 t2 t3 ...

Page 147: ... 4 6 2 TSPC 4 2 18 27 ns t9 XRD XCS ALE until XREADY early normal 17 26 ns t10 ALE until XREADY normal 2 TSPC 4 2 4 6 3 TSPC 4 2 18 27 ns t11 Pulse width XWR 10 ns t12 Hold time XCS after XWR 0 ns t13 Setup time DB before XWR 10 15 ns t14 Hold time DB after XWR 10 15 ns t15 Hold time AB after XWR 0 ns t16 XWR after ALE TSPC 4 2 ns t17 XWR XCS ALE until XREADY early normal 0 16 24 ns t18 ALE until ...

Page 148: ...ing 68HC16 In this mode all accesses are started by a falling edge at AS AB X C S R ead D B W rite D B t1 t5 D atavalid t6 t7 t13 t14 AS R W X D TAC K early X D TAC K norm al R W X D TAC K early norm al t2 t17 t4 t3 t8 t9 t10 t11 t12 t15 t16 t10 Figure 11 12 Bus Interface Timing Motorola Asynchronous ...

Page 149: ... early 0 TSPC 4 2 18 27 ns t9 AS until XDTACK early 2 T SPC 4 2 3 TSPC 4 2 18 27 ns t10 AS until XDTACK early normal 0 16 24 ns t11 XCS RWX until XDTACK normal T SPC 4 2 2 TSPC 4 2 ns t12 AS until XDTACK normal 3 T SPC 4 2 4 6 4 TSPC 4 2 18 27 ns t13 Setup time DB before AS 5 8 ns t14 Hold time DB after AS 12 18 ns t15 XCS at XDTACK early normal 18 27 ns t16 AS at XDTACK early normal T SPC 4 2 2 T...

Page 150: ...n this mode access is started by a rising edge at E clock The clock rate of the SPC 4 2 QCLK IN must be at least four times higher than that of the E clock Note If E clock 3 MHz CLK must be 24 MHz AB R ead D B W rite D B D a tavalid t2 t9 t10 t1 t4 t6 t7 E C lock t3 X C S R W t5 t8 R W Figure 11 14 Timing 68HC11 ...

Page 151: ...ock 15 22 ns t5 Hold time XCS R W to E clock 0 ns t6 XCS R W until DB low resistance 18 27 ns t7 Access time of E clock until DB valid T SPC 4 2 57 85 ns t8 XCS R W until DB high resistance 18 27 ns t9 Setup time DB before E clock 10 15 ns t10 Hold time DB after E clock 20 30 ns Table 11 15 Bus Interface Timing Motorola Synchronous Times in brackets apply for 3 3 V For write timing note the inform...

Page 152: ...PROFIBUS Controller SPC 4 2 LF 152 C79000 G8976 C157 3 ...

Page 153: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 153 Technical Specifications 12 ...

Page 154: ...3 to VDD 0 3 V Output voltage VO 0 3 to VDD 0 3 V DC output current IO see table mA DC supply current IDD ISS Approx 60 mA Ambient temperature Topt 40 to 85 C Storage temperature TBD Power loss Pmax 300 mW 5 V 12 Mbps Power loss Pmax 20 mW 3 3 V 31 25 Kbps Table 12 1 Maximum Limit Values Notice Operation over longer periods with these values reduces the service life ...

Page 155: ...tage VDD 4 5 5 5 V VSS 0V DC supply voltage VDD 3 0 3 6 V VSS 0V Input voltage VI 0 VDD V Input voltage high level VIH 0 7 VDD VDD V Input voltage low level VIL 0 0 3 VDD V Output voltage VO 0 VDD V Ambient temperature TA 40 85 C DC supply current typically 55 5 V 12 Mbps DC supply current typically 3 6 3 3 V 31 25 Kbps Table 12 2 Permitted Operating Values ...

Page 156: ... V All information on current consumption in mA Clock Frequency Mode 2 MHz 4 MHz 8 MHz 24 MHz 48 MHz Reset 0 25 0 7 1 4 2 9 5 Memory Access 4 7 11 23 43 Data exchange 9 6 Kbps 5 4 Data exchange 19 2 Kbps 4 5 Data exchange 500 Kbps 5 5 32 Data exchange 1 5 Mbps 38 Data exchange 12 Mbps 55 Data exchange 31 25 Kbps VDD 3 3 V 3 6 Table 12 3 Current Consumption The values shown in the table are typical...

Page 157: ... 3 7 V Schmitt trigger at 5 0 V Threshold voltage 1 level V 1 5 VDD V Schmitt trigger at 5 0 V Input leakage current II 1 uA Output leakage current IOZ 10 uA Output current 0 level IOL 4 1 mA 4 mA cell Output current 1 level IOH 4 2 mA 4 mA cell Output current 0 level IOL 10 1 mA 10 mA cell Output current 1 level IOH 10 2 mA 10 mA cell Short circuit current IOS TBD 3 mA Input capacitance CIN 5 pF ...

Page 158: ... Driver strength Cap load Pullup DB 0 7 I O Tristate 4 mA 50 pF min 50 kΩ RTS ADD L Tristate 4 mA 50 pF TxD O Tristate 4 mA 50 pF X INT L Tristate 4 mA 50 pF X INTCI L Tristate 4 mA 50 pF XREADY L Tristate 10 mA 50 pF XHOLD TOKEN L Tristate 4 mA 50 pF ISCLK Out L Tristate 10 mA 50 pF Table 12 5 Ratings of the Output Drivers ...

Page 159: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 159 Package 13 ...

Page 160: ...3 34 44 B A C D F G H J K L M P A 12 0 0 2 mm B 10 0 0 2 mm C 10 0 0 2 mm D 12 0 0 2 mm F typ 1 0 mm G typ 1 0 mm H 0 37 0 08 mm J 0 8 mm L 0 6 0 15 mm M 0 15 0 05 mm pin thickness P 1 4 0 15 mm θ 0 to 10 R max 1 6 mm S 0 1 0 05 mm R θ S Figure 13 1 44 Pin LQFP Package ...

Page 161: ...d for more than 48 hours without being in a dry pack In this case the component must then be dried at 125 oC for 24 hours and then processed within 48 hours Due to the solderability of the component it can only undergo this drying process once Care must also be taken to be sure that the connectors of the SPC 4 2 are not bent Problem free processing can only be guaranteed when coplanarity of the pi...

Page 162: ...Lead Finish Sn Ag During lead free infrared soldering the maximum temperature 260 C must not be exceeded on the package surface and the temperature must not exceed 230 C for a period longer than 30 to 50 seconds Figure 13 2 Example of a temperature profile ...

Page 163: ...formation as shown symbolically Figure 13 3 Manufacturer Siemens AG Type name SPC 4 2 LF Type code company internal code 190C580EF003 Production information coded production identifier allowing a batch to be identified if faults are discovered SIEMENS SPC 4 2 LF 190C580EF003 Production information Figure 13 3 Printing the SPC 4 2 LF ...

Page 164: ...n two different types of packaging Small pack pack of 5 Single Tray pack of 160 Box This type of packing is suitable for laboratories Since the positioning is not reproducible this is not suitable for automatic assembly Tray The tray is suitable for automatic assembly The dimensions are shown in Figure 13 4 ...

Page 165: ...Package PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 165 Figure 13 4 Tray Spezification ...

Page 166: ...PROFIBUS Controller SPC 4 2 LF 166 C79000 G8976 C157 3 ...

Page 167: ...r SPC 4 2 LF C79000 G8976 C157 3 167 References 14 DIN 19245 Part 1 Beuth Verlag DIN 19245 Part 2 Beuth Verlag DIN E 19245 Part 3 Beuth Verlag PNO Guidelines PROFIBUS PA PNO EN50170 Volume 2 IEC 61158 2000 Part 2 3 4 5 6 ...

Page 168: ...PROFIBUS Controller SPC 4 2 LF 168 C79000 G8976 C157 3 ...

Page 169: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 169 Addresses 15 ...

Page 170: ...PROFIBUS Controller SPC 4 2 LF 170 C79000 G8976 C157 3 15 1 PNO PROFIBUS User Organization Head Office Haid und Neu Straße 7 76131 Karlsruhe Germany Tel 0721 9658 590 Fax 0721 9658 589 ...

Page 171: ...2 LF C79000 G8976 C157 3 171 15 2 Contacts in the Interface Center Siemens AG ComDeC Correspondence to Postfach 2355 90713 Fürth House address Würzburgerstr 121 90766 Fürth Tel 0911 750 2080 Fax 0911 750 2100 E mail ComDeC fthw siemens de ...

Page 172: ...PROFIBUS Controller SPC 4 2 LF 172 C79000 G8976 C157 3 ...

Page 173: ...PROFIBUS Controller SPC 4 2 LF C79000 G8976 C157 3 173 Appendix 16 ...

Page 174: ...ux energy 3 3 V 5 V SPC 4 Siemens PROFIBUS Controller Processor of field device e g M 377 xx 80c165 80c32 8051 Local RAM Local flash SIM 1 Siemens IEC H1 Medium Attachment Unit Operating volötage Other interfaces Figure 16 1 Hardware Architecture with SIM 1 SPC 4 2 with auxiliary energy decoupling at constant current consumption additional 6 6 V ...

Page 175: ...e ALI PROFIBUS Application Layer Interface FMS PROFIBUS Fieldbus Message Specification LLI PROFIBUS Lower Layer Interface DP PROFIBUS Distributed IO Figure 16 2 System Environment of the PROFIBUS PA FMS DP Server Software Suitable server software is available from the SIMATIC NET Provider TMG ...

Page 176: ...al components are required in addition to the ASIC SIM 1 to connect modules or field devices to an intrinsically safe network for PROFIBUS PA and FF In conjunction with the SPC 4 2 the Siemens PROFIBUS controller for slave applications the functions of a PROFIBUS and FF slave can be handled optimally from the physical attachment to the communication control PROFIBUS IEC H1 Transducer Actuator Cont...

Page 177: ...icture shows one possible way of attaching the SPC 4 2 to the ASIC SIM 1 SPC 4 TxS TxE Reset RxS M Diode bridge Transistor 3 3 V 5 V M To sensor or actuator Resistor SIM 1 Figure 16 4 Application Example SIM 1 in the constant current mode with SPC 4 2 without electrical isolation ...

Page 178: ...PROFIBUS Controller SPC 4 2 LF 178 C79000 G8976 C157 3 ...

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