Siemens SAB 80515 Series, User Manual, Page: 36 / 270

Semiconductor Group 36
On-Chip Peripheral Components
lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications
(
V
IL
/
V
IH
). Since P6 is not a bit-addressable register, all input lines of P6 are read at the same time
by byte instructions.
Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care
must be taken that all bits of P6 are masked which have an undetermined value caused by their
analog function .
In order to guarantee a high-quality A/D conversion, digital input lines of port 6 should not toggle
while a neighbouring port pin is executing an A/D conversion. This could produce crosstalk to the
analog signal.
7.1.1.1 Digital I/O Port Circuitry (MYMOS/ACMOS)
Figure 7-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each
of the 6 I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which
will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The
Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the
CPU. The level of the port pin itself is placed on the internal bus in response to a "read-pin" signal
from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to
P5) activate the "read-latch" signal, while others activate the "read-pin" signal (see section 7.1.4.3).
Figure 7-1
Basic Structure of a Port Circuitry
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