
Device Specifications
Semiconductor Group
251
Notes for page 249 and 250:
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be
superimposed on the
V
OL
of ALE and ports 1, 3, 4 and 5. The noise is due to external bus
capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0
transitions during bus operation.
In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may
exceed 0.8 V.
Then, it may be desirable to qualify ALE with a Schmitttrigger, or use an address latch
with a Schmitttrigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to
momentarily fall below the 0.9
V
CC
specification when the address bits are stabilizing.
3) Power-down
I
CC
is measured with: EA = Port 0 = Port 6 =
V
CC
;
XTAL1 = N.C.; XTAL2 =
V
SS
; RESET =
V
CC
;
V
AGND
=
V
SS
; all other pins are disconnected.
4)
I
CC
(active mode) is measured with: XTAL2 driven with the clock signal according
to the figure below; XTAL1 = N.C.; EA = Port 0 = Port 6 =
V
CC
; RESET =
V
SS
; all other
pins are disconnected.
I
CC
might be slightly higher if a crystal oscillator is used.
5)
I
CC
(idle mode) is measured with: XTAL2 driven with the clock signal according to the
figure below; XTAL1 = N.C.; EA =
V
SS
; Port 0 = Port 6
V
CC
; RESET =
V
CC
; all other pins are
disconnected; all on-chip peripherals are disabled.
6)
I
CC
at other frequencies is given by:
Active mode:
I
CC max
(mA) = 2.67
×
f
OSC
(MHz) + 3.00
Idle mode:
I
CC max
(mA) = 0.88
×
f
OSC
(MHz) + 2.50
where
f
OSC
is the oscillator frequency in MHz.
I
CC max
is given in mA and measured at
V
CC
= 5 V (see also notes 4 and 5)
*
Summary of Contents for SAB 80515 Series
Page 9: ...Semiconductor Group 9 Introduction Figure 1 2 Block Diagram ...
Page 12: ...Semiconductor Group 12 Fundamental Structure Figure 2 1 Detailed Block Diagram ...
Page 18: ...Semiconductor Group 18 Central Processing Unit Figure 3 1 Fetch Execute Sequence ...
Page 73: ...Semiconductor Group 73 On Chip Peripheral Components Figure 7 25 A D Converter Block Diagram ...
Page 83: ...Semiconductor Group 83 On Chip Peripheral Components Figure 7 33 a Timer 2 Block Diagram ...
Page 215: ...Device Specifications Semiconductor Group 215 ...
Page 217: ...Device Specifications Semiconductor Group 217 Pin Configuration P LCC 68 ...
Page 219: ...Device Specifications Semiconductor Group 219 Logic Symbol ...
Page 226: ...Device Specifications Semiconductor Group 226 Figure 1 Block Diagram ...
Page 229: ...Device Specifications Semiconductor Group 229 Figure 2 Memory Address Spaces ...
Page 239: ...Device Specifications Semiconductor Group 239 Figure 4 Block Diagram of the A D Converter ...
Page 241: ...Device Specifications Semiconductor Group 241 Figure 5 Interrupt Request Sources ...
Page 242: ...Device Specifications Semiconductor Group 242 Figure 6 Interrupt Priority Level Structure ...