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S7-300 Automation System, Hardware and Installation: CPU 31xC and CPU 31x
9-28
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The table below shows how the DP CPU operating as a DP slave recognizes
operating state transitions or data exchange interruptions.
Table 9-9
Event recognition for CPUs 31x-2 DP/31xC-2 DP as the DP slave
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Bus failure interrupt
(short-circuit,
connector
unplugged)
•
Call of OB86 with the message
6WDWLRQIDLOXUH
(coming event; diagnostic address of the DP slave, assigned to
the DP slave)
•
with I/O access: Call of OB122
(I/O access error)
DP master.
RUN
→
STOP
•
Call of OB82 with the message
0RGXOHHUURU
(coming event; diagnostic address of the DP slave, assigned to
the DP slave; Variable OB82_MDL_STOP=1)
DP master
STOP
→
RUN
•
Call of OB82 with the message
0RGXOH2.
(outgoing event; diagnostic address of the DP slave, assigned to
the DP slave; Variable OB82_MDL_STOP=0)
7LS
:
When commissioning the CPU as DP slave, always program OB82 and OB86. This
helps you to recognize and evaluate the respective operating states or data
exchange errors.
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As an alternative to the MPI interface, you can program the CPU or execute the
PG's status and control functions via the PROFIBUS-DP interface. To do so, you
must enable these functions when configuring the CPU as a DP slave in
67(3
.
This is not required for CPU 300 C.
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The use of Status and Control function via the PROFIBUS-DP interface extends
the DP cycle.
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The DP-CPU operating as a DP slave provides an intermediate memory for the
PROFIBUS DP. All data exchange between the CPU as DP slave and the DP
master takes place via this intermediate memory. You can configure up to
32 address areas for this function.