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Semiconductor Group
6-70
1999-04-01
On-Chip Peripheral Components
C541U
The endpoint interrupt enable registers contain the endpoint specific interrupt enable bits. With
these bits, the endpoint specific interrupts can be individually enabled or disabled. Additionally to a
bit in an EPIEn register, the global interrupt bit EPIn in GEPIR for endpoint n and the general
endpoint interrupt bit EUEI in IEN1 and the general interrupt enable bit EA in IEN0 must be set for
the interrupt becoming active.
Endpoint Interrupt Enable Register EPIEn, n=0-4 (Address C3H) Reset Value : 00H
Bit
Function
AIEn
USB acknowledge interrupt enable
Bit AIEn enables the generation of an endpoint specific acknowledge interrupt
when bit ACKn in register EPIRn is set.
If AIEn=0, the USB acknowledge interrupt is disabled.
If AIEn=1, the USB acknowledge interrupt is enabled.
NAIEn
USB not acknowledged interrupt enable
Bit NAIEn enables the generation of an endpoint specific not acknowledged
interrupt when bit NACKn in register EPIRn is set.
If NAIEn=0, the USB not acknowledged interrupt is disabled.
If NAIEn=1, the USB not acknowledged interrupt is enabled.
RLEIEn
Read length error interrupt enable
Bit RLEIEn enables the generation of an endpoint specific read length error
interrupt when bit RLEn in register EPIRn is set.
If RLEIEn=0, the read length error interrupt is disabled.
If RLEIEn=1, the read length error interrupt is enabled.
0
Reserved for future use. For compatiblity, these bits have to be ignored in all read
accesses and written with zero in all write accesses.
DNRIEn
Data not ready interrupt enable
Bit DNRIEn enables the generation of an endpoint specific data not ready interrupt
when bit DNRn in register EPIRn is set.
If DNRIEn=0, the data not ready interrupt is disabled.
If DNRIEn=1, the data not ready interrupt is enabled.
NODIEn
No data interrupt enable
Bit NODIEn enables the generation of an endpoint specific no data interrupt when
bit NODn in register EPIRn is set.
If NODIEn=0, the no data interrupt is disabled.
If NODIEn=1, the no data interrupt is enabled.
MSB
LSB
Bit No.
7
6
5
4
3
2
1
0
EPIEn
C3H
For accessing EPIEn, SFR EPSEL must be 0nH
.
rw
rw
rw
rw
rw
rw
rw
rw
AIEn
NAIEn
RLEIEn
0
DNRIEn NODIEn EODIEn SODIEn
Summary of Contents for C541U
Page 1: ... 8 LW 026 0LFURFRQWUROOHU 8VHU V 0DQXDO http www siem ens d Sem iconductor ...
Page 7: ......
Page 21: ...Semiconductor Group 2 6 1997 10 01 Fundamental Structure C541U ...
Page 37: ...Semiconductor Group 4 6 1997 10 01 External Bus Interface C541U ...
Page 133: ...Semiconductor Group 6 88 1999 04 01 On Chip Peripheral Components C541U ...
Page 163: ...Semiconductor Group 8 8 1997 10 01 Fail Safe Mechanisms C541U ...
Page 185: ...Semiconductor Group 10 14 1997 10 01 OTP Memory Operation C541U ...