CPU Exception
103
Drive System SD4S - Hardware Description
12
Appendix
A CPU Exception
A
CPU exception
error announces a CPU error. For that purpose all 3 status LEDs flash
simultaneously. Then, the middle LED flashes once or several times to indicate a sub
error. The number of flashes may help with the diagnosis and finding the cause of error.
CPU exception and sub error are displayed repeatedly.
The drive only leaves this error mode by means of a device restart (reset). If such an
error occurs, please contact SIEB & MEYER.
CPU
STA
REG
Device status / operational status
Blue fl.
Red fl.
Blue fl.
CPU Exception (approx. 2 seconds): CPU error an-
nouncement
Sub error: usage fault
Off
1 ×
Red fl.
Off
Executed an SDIV or UDIV instruction with a divisor
of 0
Off
2 ×
Red fl.
Off
Made an unaligned memory access.
Off
3 ×
Red fl.
Off
Attempted an access to a coprocessor if the access
is denied or privileged only (configurable in CPACR).
Off
4 ×
Red fl.
Off
Attempted an illegal load of EXC_RETURN to the
PC, as a result of an invalid context, or an invalid
EXC_RETURN value.
Off
5 ×
Red fl.
Off
Attempted to execute an instruction that makes ille-
gal use of the EPSR.
Off
6 ×
Red fl.
Off
Attempted to execute an undefined instruction.
Sub error: bus fault
Off
7 ×
Red fl.
Off
Bus fault occurred during floating-point lazy state
preservation.
Off
8 ×
Red fl.
Off
Stacking for an exception entry has caused bus
fault.
Off
9 ×
Red fl.
Off
Unstack for an exception return has caused bus
fault.
Off
10 ×
Red fl.
Off
Imprecise data bus error.
Off
11 ×
Red fl.
Off
Precise data bus error.
Off
12 ×
Red fl.
Off
Error on prefetching an instruction.
Sub error: memory fault
Off
13 ×
Red fl.
Off
MemManage fault occurred during floating-point lazy
state preservation.
Off
14 ×
Red fl.
Off
Stacking error caused by ARM MPU violation.
Off
15 ×
Red fl.
Off
Unstacking error caused by ARM MPU violation.
Off
16 ×
Red fl.
Off
The processor attempted a load or store at a pro-
tected (by ARM MPU) location.
Tab. 15: CPU exception errors
