NOTE
It should be noted that some commands can only be issued once per eight clock cycles
of the IP Core (which translates to roughly 110 ns). If the user interface is designed in a
way that guarantees the read/write flags to be always set for a significantly longer time,
then the timing reference doesn’t need to be monitored.
9.4.2
Read access timing
The read access through the basic interface must be implemented according to the dia‐
gram below.
clock
hostd_r
hostd_a
hostd_do
address to read
register data
Figure 40: Read access basic interface
The register address to be read must be set at the address bus (
hostd_a
). Then the
read flag (
hostd_r
) must be set to “1”. After two clock cycles (i.e. at the second rising
edge of the
CLK
signal, max. 27 ns) the register data will be available at the data out
bus (
hostd_do
). It will be kept available for as long as the address is not changed. This
is the fastest reading procedure possible for the IP Core.
9.4.3
Write access timing
The write access through the basic interface must be implemented according to the
diagram below.
110 111 101 100 000 001 011 110 110 111
100
101
000
bit_period
hostd_w
hostd_a
hostd_di
register address
data to write
Figure 41: Write access basic interface
For write operations it is important to monitor the
bit_period
signal when implement‐
ing the fastest possible write commands. Register address and data to write to the reg‐
ister must be set on their corresponding busses (
hostd_a and hostd_di
). Then the
write flag (
hostd_w
) must be set to “1” and stay active while
bit_period
is transition‐
ing from “000” to “001”. At the time of this transition, the data in the register will be
updated with the data of the data in bus. The write flag should be kept high until
bit_period
has reached “011”.
FPGA IP-CORE
9
8017595/ZTW6/2018-01-15 | SICK
T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
149
Subject to change without notice