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AGP Master 1 WS Read
When this item enabled, reading from the AGP (Accelerated Graphics
Port) is executed with one wait state.
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The Choice: Enabled or Disabled.
DBI Output for AGP Trans
AGP 8X transfer mode only. Select Dynamic Bus Inversion function
Enable / Disable.
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The Choice: Enabled or Disabled.
CPU & PCI Bus Control
Options are in its sub-menu.
Press <Enter> to enter the sub-menu of detailed options.
PCI1 Master 0 WS Write
When this item enabled, writing to the PCI bus is executed with zero
wait state.
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The Choice: Enabled or Disabled.
PCI2 Master 0 WS Write
When this item enabled, writing to the AGP bus is executed with zero
wait state.
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The Choice: Enabled or Disabled.
PCI1 Post Write
This Item enable/disable AGP post write function, which means when
cpu accessing the AGP data, the chipset can queue the instruction
when the AGP bus is busy,then write the data when AGP bus is avail-
able .
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The Choice: Enabled or Disabled.
PCI2 Post Write
This Item enable/disable PCI post write function, which means when
cpu accessing the PCI data, the chipset can queue the instruction when
the PCI bus is busy, then write the data when AGP bus is available.
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The Choice: Enabled or Disabled.
VLink 8X Support
Enable this item will set VLink 8X transfer mode. Disable it will set
VLink 4X transfer mode.
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The Choice: Enabled or Disabled.
