Shivaki STV-24LEDGR7, Service Manual

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Figure 21. Differential input waveform timing - tIS and tIH
Figure 20. Differential input waveform timing - tDS and tDH
K4T51163QI
datasheet
DDR2 SDRAM
Rev. 1.0
K4T51083QI
K4T51043QI
20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
IH
(AC) level to the
differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V
IL
(AC) level to the differential data strobe crosspoint for
a falling signal applied to the device under test. DQS, DQS signals must be monotonic between V
IL
(DC)max and V
IH
(DC)min. See Figure 20.
21. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced from the differential data strobe crosspoint to the input sig-
nal crossing at the V
IH
(DC) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the V
IL
(DC) level for
a rising signal applied to the device under test. DQS, DQS signals must be monotonic between V
IL
(DC)max and V
IH
(DC)min. See Figure 20.
22. Input waveform timing is referenced from the input signal crossing at the V
IH
(AC) level for a rising signal and V
IL
(AC) for a falling signal applied to the
device under test. See Figure 21.
23. Input waveform timing is referenced from the input signal crossing at the V
IL
(DC) level for a rising signal and V
IH
(DC) for a falling signal applied to the
device under test. See Figure 21.
tDS
V
DDQ
V
IH
(AC)min
V
IH
(DC)min
V
REF
(DC)
V
IL
(DC)max
V
IL
(AC)max
V
SS
DQS
DQS
tDH
tDS tDH
tIS
CK
CK
tIH
tIS tIH
V
DDQ
V
IH
(AC)min
V
IH
(DC)min
V
REF
(DC)
V
IL
(DC)max
V
IL
(AC)max
V
SS
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