Shivaki STV-24LEDGR7, Service Manual

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K4T51163QI
datasheet
DDR2 SDRAM
Rev. 1.0
K4T51083QI
K4T51043QI
1. Ordering Information
NOTE :
1. Speed bin is in order of CL-tRCD-tRP
2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
2. Key Features
Org. DDR2-1066 7-7-7 DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 5-5-5 Package
128Mx4 - K4T51043QI-HC(L)E7 K4T51043QI-HC(L)F7 K4T51043QI-HC(L)E6 60 FBGA
64Mx8 - K4T51083QI-HC(L)E7 K4T51083QI-HC(L)F7 K4T51083QI-HC(L)E6 60 FBGA
32Mx16 K4T51163QI-HC(L)F8 K4T51163QI-HC(L)E7 K4T51163QI-HC(L)F7 K4T51163QI-HC(L)E6 84 FBGA
Speed DDR2-1066 7-7-7 DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 5-5-5 Units
CAS Latency 7 5 6 5 tCK
tRCD(min) 13.125 12.5 15 15 ns
tRP(min) 13.125 12.5 15 15 ns
tRC(min) 58.125 57.5 60 60 ns
•
JEDEC standard V
DD
= 1.8V ± 0.1V Power Supply
• V
DDQ
= 1.8V ± 0.1V
• 333MHz f
CK
for 667Mb/sec/pin, 400MHz f
CK
for 800Mb/sec/pin and
533MHz f
CK
for 1066Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4 , 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an
optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
-50ohm ODT
-High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than T
CASE
85
°
C, 3.9us at
85
°
C < T
CASE
< 95
°
C
• All of products are Lead-Free, Halogen-Free, and RoHS compliant
The 512Mb DDR2 SDRAM is organized as a 8Mbit x16 I/Os,16Mbit x8 I/Os,
32Mbit x4 I/Os 4banks device. This synchronous device achieves high
speed double-data-rate transfer rates of up to 1066Mb/sec/pin (DDR2-
1066) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM fea-
tures such as posted CAS with additive latency, write latency = read latency
-1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. For example, 512Mb(x8)
device receive 14/10/2 addressing.
The 512Mb DDR2 device operates with a single 1.8V ± 0.1V power supply
and 1.8V ± 0.1V V
DDQ
.
The 512Mb DDR2 device is available in 60ball FBGAs(x4/x8) and in 84ball
FBGAs(x16)
NOTE :
1. This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device Operation & Timing Dia-
gram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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