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Shivaki STV-24LEDGR7 Service Manual Download Page 138

 

 

SY8009A/SY8009B

 

 
 
  

 

SOT23-5 Package outline & PCB layout design 

 

 

    

2

.4

0

0

.8

0

0.55

0.95 TYP

2

.4

0

0

.8

0

0.55

0.95 TYP

      

 

     

1

.5

0

 -

1

.7

0

0.30 - 0.50

2.80 - 3.10

2

.7

0

 -

3

.0

0

1

.5

0

 -

1

.7

0

0.30 - 0.50

2.80 - 3.10

2

.7

0

 -

3

.0

0

 

Recommended Pad Layout 

 
 
 

0

.1

 -

0

.1

5

0

.2

5

 R

E

F

0.3 - 0.6

0

.1

 -

0

.1

5

0

.2

5

 R

E

F

0.3 - 0.6

         

1.0 - 1.3

0.

01

 -

0.

1

1.90 TYP

0.95 TYP

1.0 - 1.3

0.

01

 -

0.

1

1.90 TYP

0.95 TYP

 

 
           

 

Notes:  All dimensions are in millimeters. 
 

All dimensions don’t include mold flash & metal burr. 

 
 
 

 
 
 

Page 122 of 152

Summary of Contents for STV-24LEDGR7

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Page 8: ...ESET LOW GPIO_AB24 S2 MODER CONTOL LED STATE PM6 GPIO_AC4 RF_AGC switch o RF AGC control At the DVB Please set hight ATV set low for RF AGC DVD TXD O communications I control ANT POWER ANT POWER 0 Low Off 1 HIGT ON GPIO_K4 GPIO_AC11 GPIO_AB7 O AMP STB Control amp STBl DIGITAL AUDIO OUT PUT GPIO_P5 SPDIF O GPIO_T4 SEL_DVD YPBPR O I DVD RXD DVD communications GPIO_E6 SYSTEM POWER System PWR ON O 0 T...

Page 9: ...P 2 0MM CON8 2 0 W CN2 CON8 DIP 2 0MM CON8 2 0 W C221 2 2uF C0805 C221 2 2uF C0805 R3 12R R0402 R3 12R R0402 C22 0 1u C0402 C22 0 1u C0402 R18 10K 0402 5 R0402 R18 10K 0402 5 R0402 R28 1K R0402 R28 1K R0402 C1 100nF X7R C0402 C1 100nF X7R C0402 R37 2k R0402 R37 2k R0402 C12 100nF C0402 C12 100nF C0402 C32 0 1u C0402 C32 0 1u C0402 R31 10K R0402 R31 10K R0402 R5 100K R0402 R5 100K R0402 C9 100nF C0...

Page 10: ...R80 100K R80 100K R48 2 2K R48 2 2K A0 1 A1 2 A2 3 GND 4 SDA 5 SCL 6 WP 7 VCC 8 U9 24C32 NC U9 24C32 NC 1 2 3 4 8 7 6 5 RN2 22R RN2 22R R76 10k R76 10k L10 120nH L10 120nH 1 2 3 4 8 7 6 5 RN9 22R RN9 22R R73 10K NC R73 10K NC 1 2 3 4 8 7 6 5 RN10 22R RN10 22R R60 22R R60 22R 1 2 D4 ESD 0402 D4 ESD 0402 PAD_PCM_D 0 W21 PAD_PCM_D 1 U21 PAD_PCM_D 2 U19 PAD_PCM_D 3 AD12 PAD_PCM_D 4 AC12 PAD_PCM_D 5 AD...

Page 11: ...RPS0402 1 2 3 4 8 7 6 5 RN33 22R RP0402 RN33 22R RP0402 R108 100R R0402 R108 100R R0402 1 2 3 4 8 7 6 5 RN34 22R RPS0402 RN34 22R RPS0402 1 2 3 4 8 7 6 5 RN37 75R RPS0402 RN37 75R RPS0402 Vdd A1 NC A2 Vss A3 DQ14 B1 VssQ B2 UDM B3 A4 N8 A6 N7 Vdd M9 A0 M8 A2 M7 CS L8 CAS L7 ODT K9 CLK K8 RAS K7 Vdd J9 CLK J8 VssDL J7 DQ5 H9 VssQ H8 DQ2 H7 VddQ G9 DQ0 G8 VddQ G7 DQ7 F9 VssQ F8 LDQS F7 VddQ E9 LDQS ...

Page 12: ...UF C163 10UF C115 1000pF C115 1000pF C143 56pF C143 56pF C107 100nF_X7R C107 100nF_X7R E14 470uF 16V NC E14 470uF 16V NC C146 1000pF C146 1000pF R125 4 7K R125 4 7K C91 0 1u C91 0 1u C161 1000pF C161 1000pF C102 1uF Y5V 16V 0603 C102 1uF Y5V 16V 0603 ANT_VDD 1 RF_AGC 3 NC 7 SCL 4 SDA 5 5VB2 6 5VB1 2 AS 8 IF_AGC 9 PIF 10 PIF 11 IF ATV 12 GND 13 GND 14 GND 15 GND 16 TN1 LG NC TN1 LG NC C97 47n C97 4...

Page 13: ... July 13 2010 Title Size Document Number Rev Date Sheet of MSD309 V7 0 A 05 pcmcia 深圳市鼎科实业有限公司 B 6 9 Tuesday July 13 2010 Title Size Document Number Rev Date Sheet of MSD309 V7 0 A 05 pcmcia 深圳市鼎科实业有限公司 B 6 9 Tuesday July 13 2010 PWR CTRL DVB T2 TUNER Optional C164 0 1u C164 0 1u R159 100R R159 100R C165 NC 100nF C165 NC 100nF R164 NC 1K R164 NC 1K R162 NC 10k R162 NC 10k TP27 TP27 TP25 TP25 TP24 ...

Page 14: ...K R207 0R R207 0R D34 ESD 0402 D34 ESD 0402 R189 10K R189 10K R186 10K R186 10K R175 0R R175 0R R212 10K R212 10K D21 ESD 0402 D21 ESD 0402 D9 ESD 0402 D9 ESD 0402 R204 0R R204 0R D27 ESD 0402 D27 ESD 0402 R190 1K R190 1K D18 ESD 0402 D18 ESD 0402 D12 ESD 0402 D12 ESD 0402 D15 ESD 0402 D15 ESD 0402 D23 ESD 0402 D23 ESD 0402 R202 0R R202 0R R171 0R R171 0R R193 10K R193 10K R177 0R R177 0R Q20 MMBT...

Page 15: ...200ma 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 21 24 25 CN14 SCART NC SCART_0 CN14 SCART NC SCART_0 T9 T9 R215 0R R215 0R R289 10K DVD R289 10K DVD C175 200pF C175 200pF C188 47n C188 47n R255 68R R255 68R D52 ESD 0402 D52 ESD 0402 C181 1uF 10V C181 1uF 10V ZD2 ESD ZD2 ESD TP33 TP33 C202 47n C202 47n R235 68R R235 68R D67 NC ESD 0402 D67 NC ESD 0402 1 2 D69 ESD 0402 D69 ESD 0402 C192 47n...

Page 16: ...T8 B1 3_5mm_8v ia C235 1uF 16V 0603 X AMP C235 1uF 16V 0603 X AMP C242 100NF C242 100NF E21 220uF 16V E21 220uF 16V R359 220R 0603 R359 220R 0603 R332 4 7K R332 4 7K 4 5 6 7 9 1 2 3 8 MT8 B2 3_5mm_8v ia MT8 B2 3_5mm_8v ia 1 2 R348 22K R348 22K R307 0R R307 0R 1 2 3 Q27 MMBT3904 Q27 MMBT3904 1 2 R342 22K R342 22K E19 470uF 16V 1517 E19 470uF 16V 1517 R354 4 7K R354 4 7K C241 1uF 16V 0603 X AMP C241...

Page 17: ...e 8 to 10 Circuit Diagram page 11 to 18 Main IC Specifications page 19 to 131 PCB Information page 132 to 143 Software Upgrade page 144 to 148 MSD306 Factory Menu page 149 to 152 This manual is the latest at the time of printing and does not include the modification which may be made after the printing by the constant improvement of product Page 1 of 152 ...

Page 18: ...ian should open the case of the LCD TV monitor adapter z Never use your LCD TV monitor adapter if the power cord has been damaged Do not allow anything to reston the power cord and keep the cord away from place where people can trip over it z Be sure to hold the plug not the cord when disconnecting the adapter from an electric socket z Openings in the LCD TV monitor adapter cabinet are provided fo...

Page 19: ...rect sunlight and keep it away from heaters stoves fireplaces and other sources of heat z Unplug the DC adapter when it is going to be left unused for an extended period of time z To reduce the risk of fire or electric shock and annoying interference use the recommended accessories only z IF the LCD TV monitor is broken do not try to repair it yourself Contact qualified service personnel z Unplug ...

Page 20: ...BY REVISIONS ISSUED DATE DESCRIPTION RAISED BY SPECIFICATION AGREED SIGNATURE DATE R D DEPARTMENT COMMERCIAL DEPARTMENT PRODUCTION DEPARTMENT Q A DEPARTMENT CUSTOMER SPECIFICATION APPROVED SIGNATURE DATE NOTE Only documents stamped Controlled Document to be used for manufacture of production parts Page 4 of 152 ...

Page 21: ...58 NTSC4 43 Yes VHF L E2 S10 48 25 168 25MHz VHF H E5 S41 175 25 463 25MHz Analog Channel Coverage For SECAM BG DK PAL BG DK I UHF E21 E69 471 25 855 25MHz Yes VHF L FA F 47 75 164 75MHz VHF H F1 Q 176 00 296 75MHz Analog Channel Coverage For SECAM L UHF 21 69 471 25 855 25MHz Yes DVB T Channel Coverage VHF L VHF H UHF 174MHZ 862MHZ Yes PAL BG I DK SECAM BG DK L 38 9MHZ SECAM L 33 95MHZ Picture I ...

Page 22: ...et Optional Connector Interface Headphone Φ3 5 Jack Yes Audio AMP Output Power Max 7 0W 2 Number of Speaker 2 NICAM A2 STEREO Yes Audio Tone with base Treble Balance Yes VHF 48dB Yes Video sensitivity at 30dB S N UHF 51dB Yes FM for BG DK I 35dB Yes Sound sensitivity at 30dB S N Am for L L 39dB Yes Synchronizing Sensitivity 35dB Yes Color Sensitivity 38dB Yes Teletext Sensitivity 50dB Yes NICAM Th...

Page 23: ...at PAL or SECAM CVBS S Video 16 9 4 3 Mode Yes Main Electrical Specification For DVB T Section Audio Format MPEG 1 MPEG 2 Layer Ⅰ Ⅱ Yes On working 60W Max Power Consumption Standby 0 5W TELETEXT 750 Pages for Western Eastern Europe Yes Operating Temperature Range 0 TO 40 Dimension mm TBA Net Weight Gross Weigh TBA Packing TBA Accessories User Manual Remote Control Power line Specification are subj...

Page 24: ...lock 5V 3 3V 5V 3 3V 2 5V 1 8V 5V 3 3V 1 32V 5V 5V 12V 12V P MOS DVD POWER AUDIO AMP VIF AMP P MOS LDO PANNEL MSD306 DC DC MSD306 DC DC LDO IN4001 MSD306 DDR MSD306 LDO MAX3543 DVD MAIN BOARD 12V DC DC DC DC DC P MOS Page 8 of 152 ...

Page 25: ...TOR REMOTE INSTRUCTION BACK LIGHT CONNECTOR SPDIF C I 2 MSD306 SCART DDR 1 FLASH LVDS CONTOLLOR CONNECTOR ADDRESS CONTROLLOR CI PCMICA TUNER MAX3543 SAW SAW HDMI HDMI VGA YPBPR AV Earphone USB DATA AUDIO L R MUTE AUDIO AMP R2A15120 SPEAKER R L VIF AIF DIF DIF Page 9 of 152 ...

Page 26: ...BLOCK DIAGRAM DVD System Block Diagram Page 10 of 152 ...

Page 27: ...c FB 0 1uF BC26 0 1uF BC26 0 1uF BC13 0 1uF BC13 TP6c F TP6c F BC16 0 1u BC16 0 1u TP10c TP10c U3 RCRTOO2SL U3 RCRTOO2SL POWER_1 1 IN_1 2 OUT_2 3 POWER_2 4 IN_2 5 OUT_1 6 R31 0 R31 0 0 1uF BC21 0 1uF BC21 R50 4 7 R50 4 7 R52 4 7K R52 4 7K 0 1uF BC32 0 1uF BC32 0 1uF BC14 0 1uF BC14 R41 1K R41 1K R44 0 R44 0 0 1uF BC20 0 1uF BC20 R28 0 R28 0 R38 75 R38 75 R46 180K R46 180K 0 1uF C35 0 1uF C35 EC11 ...

Page 28: ...FB L4 FB L1 FB L1 NJM4558 U1A NJM4558 U1A 3 2 1 8 4 R110 100R R110 100R 1N4001 D1 1N4001 D1 0 1uF BC1 0 1uF BC1 10pF C15 10pF C15 R107 0R R107 0R R11 33K R11 33K 100pF C18 100pF C18 0 1uF BC3 0 1uF BC3 FB L5 FB L5 10uF 10V C11 10uF 10V C11 R12 9 1K R12 9 1K 0 1uF BC5c 0 1uF BC5c 100uF 16V EC5 100uF 16V EC5 R102 0R R102 0R 10uF 10V C4 10uF 10V C4 POWER CN4 POWER CN4 1 2 3 4 5 KEY CN1 KEY CN1 1 2 3 ...

Page 29: ... 3 4 4 5 5 6 6 7 7 8 8 9 9 H12 NC 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 H14 NC R119 2 2K R118 2 2K C42 47n_X7R C40 330pF R50 75R R48 33R C34 330pF C38 330pF C35 1uF C37 1uF R42 560 R40 560 R43 680 R41 680 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 H10 NC S1 1 2 3 4 5 CN2 5P2 0mm D38 1N4001 R393 1K R660 100K R658 1k R397 1K R659 100R C853 100nF DD40 BAT54C R713 1k R708 4 7k R711 100K R715 1K R716 10k Q57 MM...

Page 30: ...1M M2 PADA_BIN1P R3 PADA_RIN2P P1 PADA_GIN2P N2 PADA_BIN2P T1 PADA_CVBS0 V2 PADA_CVBS4 T3 PADA_CVBS5 T2 PADA_CVBS_OUT1 U1 PADA_VCOM U3 PADA_CVBS2 U2 PADA_CVBS1 U4 PADA_CVBS_OUT2 U2 E MSD306 PWM SAR SPI UART I2CS I2CM LVDS GPIO_PM IR XTAL RESET GPIO_TCON USB AA20 PADA_OUTN_CH 6 _PAD_R_ODD 6 _ AA19 PADA_OUTP_CH 6 _PAD_R_ODD 7 _ W18 PADA_OUTN_CH 7 _PAD_R_ODD 4 _ AA18 PADA_OUTP_CH 7 _PAD_R_ODD 5 _ Y18...

Page 31: ...90R R434 1k R425 1K R417 4 7K R440 100R R421 56R R479 10K C87 100nF C85 100nF C86 100nF C89 100nF L42 NC 2 2uH L405 0 82uH Q401 3904 C469 0 1u C467 10n C463 10n Q405 2SC2216 SAW ING OUT1 GND OUT2 IN U30 F438901 SAW ING OUT1 GND OUT2 IN U27 F938908需确认 CA20 100uF 16V R29 10k R37 10K R39 1K R44 10k DD7 NC DD12 NC DD13 ESD 0402 DD20 ESD 0402 DD21 NC DD22 NC DD23 NC DD24 NC DD25 NC DD26 NC R72 10K Q1 3...

Page 32: ... R66 47R C70 330pF R93 27k R94 27K R75 27K R76 27K 1 2 3 Q17 MMBT3904 R142 220R 1 2 3 Q21 MMBT3904 R143 220R R L 1 4 3 RO 5 LO 2 J4 CKX 3 5 01 RE6 OPEN RE1 OPEN RE2 OPEN DD27 DD28 DD29 DD31 DD32 C79 47n C80 47n C112 47n C113 47n C114 47n C116 1n C119 47n R232 75R R173 6 8K R199 1K R200 68R R202 33R R207 33R R209 0R R211 68R R217 33R R218 68R R219 75R R220 75R R221 75R 2 4 6 8 10 12 14 16 18 20 1 3...

Page 33: ... CT40 1000pF CT19 1000pF RT14 0 CT32 1000pF CT31 1000pF CT36 0R CT37 0R CT7 4 7uF CT8 47pF CT4 1000pF RT4 33 RT5 33 CT2 39pF CT3 39pF RT10 1k CT41 100NF CT1 1OOOPF J11 CT28 22pF YT1 24MHZ RT1 0R RT2 0R RT3 0R CT29 8 2pF NC CT34 NC CT35 NC CT39 5 6pF RT7 15R CT45 2 2uF CT12 39pF LT2 470nH CT11 68pF LT3 470nH CT13 82pF RT8 75R RT9 75R RT15 NC CT33 NC LT12 nc 15 BODY 16 BODY 3 RF_AGC 4 SCL 6 B2 5 SDA...

Page 34: ...R431 NC 68K C21 NC 1uF C221 1uF C213 1uF C216 1uF C217 1uF 16V 0603 X E20 470uF 16V NC E21 470uF 16V NC E19 1000uF 16V NC R494 NC R470 NC R471 NC R489 22K 1 2 R453 4 7K 1 2 R454 0R 1 2 R450 10K 1 2 R466 10K 1 2 R467 6 8K 1 2 R452 6 8K 1 2 3 4 CN34 CON4 2 54MM 1 2 3 Q46 3904 1 2 3 Q44 3904 1 2 3 Q5 3904 1 VSA1 2 STBYL 3 MUTEL 4 INA1 5 INB1 6 GND 7 AVCC 8 INB2 9 INA2 10 VREF 11 PROT 12 VSA2 13 OUTA2...

Page 35: ...MAIN IC SPECIFICATIONS Page 19 of 152 ...

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Page 43: ...tor terminal for protection mode Built in protection circuit for prior warning of over temperature Settable power limit value of maximum output by external resistor Adjustable carrier frequency by external resistor Selectable gain value at four stage by setting two terminals Package 48 pins HTQFP Body 7x7mm Lead pitch 0 5mm Note This amplifier s continuous maximum power is 15W 8ohm As more than 15...

Page 44: ...0 42 44 45 43 46 3 7 5 6 4 9 8 10 1 2 11 12 20 18 19 17 15 14 16 13 24 22 23 21 34 30 32 31 33 28 29 27 36 35 26 25 47 48 38 37 VDB1 OUTA1 HBA1 HBB1 OUTB1 VDA1 OUTB1 OUTA1 VDB1 VDA1 VSA1 INB1 INB2 AVCC GND MUTEL STBYL PROT VSA2 VREF OUTB2 VDB2 OUTA2 HBA2 VDA2 HBB2 OUTB2 NC NC VDA2 OUTA2 VDB2 RREF DVDD RLMT CLK GAIN1 GAIN2 ROSC VSB1 TEST1 TEST2 VSB2 INA1 INA2 NC NC VD Gain Gain 5V Reg AVCC 2 Over t...

Page 45: ... Power supply for power output stage VD is supplied VDB2 21 N C 20 CH2 B block Capacitor connection terminal for bootstrap on H side HBB2 19 CH2 A block Capacitor connection terminal for bootstrap on H side HBA2 18 N C 17 CH2 A block Power supply for power output stage VD is supplied VDA2 16 CH2 A block Power output terminal O OUTA2 14 CH2 A block Power output terminal O OUTA2 13 CH2 A block Groun...

Page 46: ...age Parameter Tj HBmax VDmax Symbol Terminal name In parentheses pin number 1 VDA1 45 46 VDB1 39 40 VDA2 15 16 VDB2 21 22 2 HBA1 43 HBB1 42 HBA2 18 HBB2 19 3 OUTA1 47 48 OUTB1 37 38 OUTA2 13 14 OUTB2 23 24 Note1 Momentary peak voltage near the power Tr block 1 Please design the voltage of PWM output terminal OUT1 OUT2 as below overshoot maximum 28V undershot maximum 4 5V The very big ringing volta...

Page 47: ...o consideration When you use it please take notice the stability of supply voltage that each terminal power dose not exceed rated value This product includes a MOS transistor and a CMOS logic circuit Since there are possibilities to be occurred destruction or latch up in MOS transistor or CMOS logic circuit please be careful of use same as a MOS transistor or the CMOS logic LSI About the range of ...

Page 48: ...P board mounting Exposed Die pad solder connection Using an ideal Heat Sink θjc 17 86 ºC W Simulation value 1 Board specification 1 Material Glass epoxy 2 Size 75 x 82 mm Wiring specification of 1 2 layer 1 Material Copper 2 Thickness t 35mm 150 25 75 7 00W Ta Pd 4 20W 0W 3 78W 2 27W θja 33 1 ºC W Evaluated value Measured by Renesas R2A15120FA EVB 1 Board specification 1 96W 3 47W Warning of over ...

Page 49: ... Mute Attenuation dB 67 ｄVD 400mVrms f 1KHz Ripple Rejection Ratio 90 Po 15W 15W THD 10 Power Efficiency uVrms 150 60 A Weighted filter Noise W ch 15 THD 10 Output power 0 02 Po 1W Total Harmonic Distortion Noise A 7 5 Over current detection 120 Releasing Thermal Shut down Temperature of protection release uA 10 0 Stand by MAX TYP 8 0 60 7 0 36 V mA Unit 6 5 MIN DVDD terminal voltage No Signal Con...

Page 50: ...dB GAIN Value GAIN1 H G4 L H L Terminal G3 G2 G1 Symbol GAIN Item The total gain of this system can be set to four stages with the terminal of GAIN1 and GAIN2 Input stage Power stage BTL output stage Gain structure chart Description for one CH OUTA HBA VDA VSA OUTB VDB VSB HBB PWM Gen PWM Gen VD Control logic INA GAIN1 GAIN2 INB A Terminal GAIN setting H OPEN L Connect to RREF Page 34 of 152 ...

Page 51: ...ry This circuit limits the maximum amplitude after gain setting stage Please refer to 11 1 Gain Setting for gain setting Fig 11 1 Clip output power Input signal voltage Fig 11 2 Clip output voltage VLMT RLMT LIMIT RREF AVCC Resistance value for setting maximum output power RLMT VLMT setting circuit Differential input Normal Operation Normal Operation H H Duty 50 Mute L H Hi Z Standby L L Output FE...

Page 52: ...lti channel Rosc AVCC IC2 Slave AVCC CLK ROSC OSC 11 5 Carrier frequency A standard clock carrier of the PWM signal generation is adjustable by controlling external resistor connected to terminal ROSC Carrier I O condition is controllable by external condition of terminal ROSE Carrier frequency can be set from 400kHz to 600kHz by terminal ROSC 34pin The recommended carrier frequency is 500kHz Plea...

Page 53: ...es output pins connect GND by pull down resistor 5kΩ to prevent the IC from being destructed The restoring from a protection is performed automatically The time Tpro from protection state to normal mode is decided by built in capacitance value 0 54sec The state of unusual operation can be confirmed with the terminal PROT Protection L Detect H Normal L Detect MUTEL Input signal 0V AVCC Normal Opera...

Page 54: ...EL at the intermediate voltage that is neither H nor L constantly Especially please switch STBYL instantaneously so as not to cause chattering Tpro is defined by built in capacitance value of internal timer Tpro 0 54sec In addition prevent from POP noise please design the value of coupling capacitor for analog input satisfying following condition 1 Condition 1 It is necessary to charge the couplin...

Page 55: ...0V typ 2 Over Temperature Protection Circuit This circuit detects unusual over temperature of IC chip and protects it When internal junction temperature reaches to standard temperature 150 C the operation will start And until temperature falls to the hysteresis condition 30 protection circuit will continue to be operated Protection Start Temperature 150 C typ Protection Restore Temperature 120 C t...

Page 56: ... easy to accumulate heat into the IC under load short or another stress conditions In that situation there is a possibility to bring about destruction power Tr 3 Treatment of Analog ground pin In order to reduce the interference with low level signal ground from output stage ground Vs terminal of each bridge please connect low level signal ground to power feed point separately 4 Prevention against...

Page 57: ...her party under this document by implication estoppel or other wise Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply For updates o...

Page 58: ...K4T51163QI datasheet DDR2 SDRAM Rev 1 0 K4T51083QI K4T51043QI Revision History Revision No History Draft Date Remark Editor 1 0 First Spec Release Mar 10 S H Kim Page 42 of 152 ...

Page 59: ...operating Conditions SSTL_1 8 12 7 2 Operating Temperature Condition 13 7 3 Input DC Logic Level 13 7 4 Input AC Logic Level 13 7 5 AC Input Test Conditions 13 7 6 Differential input AC logic Level 14 7 7 Differential AC output parameters 14 8 ODT DC electrical characteristics 14 9 OCD default characteristics 15 10 IDD Specification Parameters and Test Conditions 16 11 DDR2 SDRAM IDD Spec Table 18...

Page 60: ...age Refresh Period 7 8us at lower than TCASE 85 C 3 9us at 85 C TCASE 95 C All of products are Lead Free Halogen Free and RoHS compliant The 512Mb DDR2 SDRAM is organized as a 8Mbit x16 I Os 16Mbit x8 I Os 32Mbit x4 I Os 4banks device This synchronous device achieves high speed double data rate transfer rates of up to 1066Mb sec pin DDR2 1066 for general applications The chip is designed to comply...

Page 61: ...r and ground for the DLL A B C D E F G H J K L VDD NC VSS NC VSSQ DM VDDQ VDDQ VDDQ VSSQ VSSQ DQS DQS NC DQ0 VDDQ DQ2 VSSQ NC VSSDL VDD CK RAS CK CAS CS A2 A6 A4 A11 A8 NC A13 NC A12 A9 A7 A5 A0 VDD A10 AP VSS VDDQ VSSQ DQ1 DQ3 NC VDDL A1 A3 BA1 VREF VSS CKE WE BA0 VDD VSS ODT NC 1 2 3 7 8 9 Ball Locations x4 1 2 3 4 5 6 7 8 9 A B C D E F G H J K L Populated Ball Depopulated Ball Top View See the ...

Page 62: ... function of DM or RDQS RDQS are enabled by EMRS command 4 VDDL and VSSDL are power and ground for the DLL A B C D E F G H J K L VDD NU VSS DQ6 VSSQ VDDQ VDDQ VDDQ VSSQ VSSQ DQS DQS DQ7 DQ0 VDDQ DQ2 VSSQ DQ5 VSSDL VDD CK RAS CK CAS CS A2 A6 A4 A11 A8 NC A13 NC A12 A9 A7 A5 A0 VDD A10 AP VSS VDDQ VSSQ DQ1 DQ3 DQ4 VDDL A1 A3 BA1 VREF VSS CKE WE BA0 VDD VSS DM RDQS RDQS NC ODT 1 2 3 7 8 9 Ball Locati...

Page 63: ... NC VSS DQ6 VSSQ LDM VDDQ VDDQ VDDQ VSSQ VSSQ LDQS LDQS DQ7 DQ0 VDDQ DQ2 VSSQ DQ5 VSSDL VDD CK RAS CK CAS CS A2 A6 A4 A11 A8 NC NC NC A12 A9 A7 A5 A0 VDD A10 AP VSS VDDQ VSSQ DQ1 DQ3 DQ4 VDDL A1 A3 BA1 VREF VSS CKE WE BA0 VDD VSS VDD NC VSS DQ14 VSSQ UDM VDDQ VDDQ VSSQ DQ9 DQ11 DQ12 VDDQ VDDQ VSSQ VSSQ UDQS UDQS DQ15 DQ8 VDDQ DQ10 VSSQ DQ13 NC ODT M N P R 1 2 3 7 8 9 1 2 3 4 5 6 7 8 9 A B C D E F ...

Page 64: ...0 80 7 50 0 10 0 80 1 60 0 95 1 90 9 50 0 10 7 50 0 10 0 50 0 05 0 10MAX 0 35 0 05 1 10 0 10 A1 INDEX MARK A1 Datum A Datum B MOLDING AREA A B 1 2 3 4 5 6 7 8 9 0 80 x 10 8 00 B C D E F G H J K L A 0 80 x 8 6 40 60 0 45 Solder ball 0 2 M A B Post reflow 0 50 0 05 Units Millimeters Bottom Top Page 48 of 152 ...

Page 65: ... 10 1 2 3 4 5 6 7 8 9 3 20 0 80 1 60 0 95 1 90 0 50 0 05 0 10MAX 0 35 0 05 1 10 0 10 5 60 A1 INDEX MARK Datum A Datum B MOLDING AREA A B 0 80 x 14 11 20 0 80 x 8 6 40 12 50 0 10 7 50 0 10 A1 B C D E F G H K L N A J M P R 84 0 45 Solder ball 0 2 M A B Post reflow 0 50 0 05 Bottom Top Units Millimeters Page 49 of 152 ...

Page 66: ...n both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loading For x8 device the function of DM or RDQS RDQS is enabled by EMRS command BA0 BA1 Input Bank Address Inputs BA0 BA1 and BA2 define to which bank an Active Read Write or Precharge command is being applied Bank address also determines if the mode register or extended mode register is to be accessed durin...

Page 67: ...rge A10 AP A10 AP A10 AP Row Address A0 A12 A0 A12 A0 A12 Column Address A0 A9 A11 A0 A9 A0 A8 Configuration 256Mb x4 128Mb x 8 64Mb x16 of Bank 8 8 8 Bank Address BA0 BA2 BA0 BA2 BA0 BA2 Auto precharge A10 AP A10 AP A10 AP Row Address A0 A13 A0 A13 A0 A12 Column Address A0 A9 A11 A0 A9 A0 A9 Configuration 512Mb x4 256Mb x 8 128Mb x16 of Bank 8 8 8 Bank Address BA0 BA2 BA0 BA2 BA0 BA2 Auto prechar...

Page 68: ...ere is no specific device VDD supply voltage requirement for SSTL 1 8 compliance However under all conditions VDDQ must be less than or equal to VDD 1 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 2 Peak to peak AC ...

Page 69: ...information related to VPEAK value Refer to overshoot undershoot specification in device operation and timing datasheet maximum peak ampli tude allowed for overshoot and undershoot 7 5 AC Input Test Conditions NOTE 1 Input waveform timing is referenced to the input signal crossing through the VIH IL AC level applied to the device under test 2 The input signal minimum slew rate is to be maintained ...

Page 70: ...C output parameters Symbol Parameter Min Max Units NOTE VOX AC AC differential cross point voltage 0 5 VDDQ 0 125 0 5 VDDQ 0 125 V 1 NOTE 1 The typical value of VOX AC is expected to be about 0 5 VDDQ of the transmitting device and VOX AC is expected to track variations in VDDQ VOX AC indicates the volt age at which differential output signals must cross 8 ODT DC electrical characteristics NOTE Te...

Page 71: ...from DC to DC is equal to or greater than the slew rate as measured from AC to AC This is guaranteed by design and characterization 6 This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty Output slew rate load 7 DRAM output slew rate specification applies to 667Mb sec pin and 800Mb sec pin speed bins 8 Timing sk...

Page 72: ...N Exit MRS 12 0 mA Slow PDN Exit MRS 12 1 mA IDD3N Active standby current All banks open tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING mA IDD4W Operating burst write current All banks open Continuous burst writes BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE ...

Page 73: ...ollowing parameters are utilized Detailed IDD7 The detailed timings are shown below for IDD7 Legend A Active RA Read with Autoprecharge D Deselect IDD7 Operating Current All Bank Interleave Read operation All banks are being interleaved at minimum tRC IDD without violating tRRD IDD and tFAW IDD using a burst length of 4 Control and address bus inputs are STABLE during DESELECTs IOUT 0mA Timing Pat...

Page 74: ...F 25 25 25 mA IDD3P S 10 10 10 mA IDD3N 37 37 34 mA IDD4W 73 73 65 mA IDD4R 90 92 80 mA IDD5 81 80 80 mA IDD6 8 8 8 mA IDD7 124 124 115 mA Symbol 64Mx8 K4T51083QI Unit Notes 800 CL 5 800 CL 6 667 CL 5 CE7 CF7 CE6 IDD0 54 53 50 mA IDD1 62 62 60 mA IDD2P 8 8 8 mA IDD2Q 23 23 23 mA IDD2N 27 27 27 mA IDD3P F 25 25 25 mA IDD3P S 10 10 10 mA IDD3N 36 37 34 mA IDD4W 74 74 66 mA IDD4R 96 97 86 mA IDD5 81 ...

Page 75: ...0 CL 6 667 CL 5 CF8 CE7 CF7 CE6 IDD0 75 67 67 65 mA IDD1 85 80 80 75 mA IDD2P 8 8 8 8 mA IDD2Q 27 25 25 25 mA IDD2N 35 30 30 30 mA IDD3P F 31 28 28 28 mA IDD3P S 10 10 10 10 mA IDD3N 45 40 40 38 mA IDD4W 110 95 95 85 mA IDD4R 160 130 130 115 mA IDD5 90 90 90 90 mA IDD6 8 8 8 8 mA IDD7 205 200 200 185 mA Page 59 of 152 ...

Page 76: ...ins CDI x 0 25 x 0 25 x 0 25 pF Input output capacitance DQ DM DQS DQS CIO 2 5 3 5 2 5 3 5 2 5 3 5 pF Input output capacitance delta DQ DM DQS DQS CDIO x 0 5 x 0 5 x 0 5 pF Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units Refresh to active Refresh command time tRFC 75 105 127 5 195 327 5 ns Average periodic refresh interval tREFI 0 C TCASE 85 C 7 8 7 8 7 8 7 8 7 8 μs 85 C TCASE 95 C 3 9 3 9 3 9 3 9 ...

Page 77: ... max tAC min tAC max tAC min tAC max ps 18 40 DQ low impedance time from CK CK tLZ DQ 2 tAC min tAC max 2 tAC min tAC max 2 tAC min tAC max ps 18 40 DQS DQ skew for DQS and associated DQ signals tDQSQ x 175 x 200 x 240 ps 13 DQ hold skew factor tQHS x 250 x 300 x 340 ps 38 DQ DQS output hold time from DQS tQH tHP tQHS x tHP tQHS x tHP tQHS x ps 39 DQS latching rising transitions to associated cloc...

Page 78: ...command tXARD 3 x 2 x 2 x nCK 1 Exit active power down to read command slow exit lower power tXARDS 10 AL x 8 AL x 7 AL x nCK 1 2 CKE minimum pulse width HIGH and LOW pulse width tCKE 3 x 3 x 3 x nCK 27 ODT turn on delay tAOND 2 2 2 2 2 2 nCK 16 ODT turn on tAON tAC min tAC max 2 575 tAC min tAC max 0 7 tAC min tAC max 0 7 ns 6 16 40 ODT turn on Power Down mode tAONPD tAC min 2 3 tCK tAC max 1 tAC...

Page 79: ...spoint of the true e g DQS and the complement e g DQS signal 2 Slew Rate Measurement Levels a Output slew rate for falling and rising edges is measured between VTT 250 mV and VTT 250 mV for single ended signals For differential signals e g DQS DQS output slew rate is measured between DQS DQS 500 mV and DQS DQS 500 mV Output slew rate is guaranteed by design but is not necessarily tested on each de...

Page 80: ...ote that when differential data strobe mode is disabled via the EMRS the complementary pin DQS must be tied externally to VSS through a 20 Ω to 10 kΩ resistor to insure proper operation 5 AC timings are for linear signal transitions See Specific Notes on derating for other signal transitions 6 All voltages are referenced to VSS 7 These parameters guarantee device behavior but they are not necessar...

Page 81: ...ntial data strobe Table 2 DDR2 667 800 1066 tDS tDH derating with differential data strobe ΔtDS ΔtDH Derating Values of DDR2 400 DDR2 533 ALL units in ps the note applies to entire Table DQS DQS Differential Slew Rate 4 0 V ns 3 0 V ns 2 0 V ns 1 8 V ns 1 6 V ns 1 4V ns 1 2V ns 1 0V ns 0 8V ns ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH DQ Siew rate V ...

Page 82: ...he actual signal is always later than the nominal slew rate line between shaded dc level to VREF DC region use nominal slew rate for derating value see Figure 11 for differential data strobe and Figure 12 for single ended data strobe If the actual signal is earlier than the nominal slew rate line any where between shaded dc to VREF DC region the slew rate of a tangent line to the actual signal fro...

Page 83: ...K4T51083QI K4T51043QI VSS tDS tDH Setup Slew Rate Setup Slew Rate Rising Signal Falling Signal ΔTF ΔTR VREF DC VIL AC max ΔTF VIH AC min VREF DC ΔTR VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max nominal slew rate nominal slew rate VREF to ac region VREF to ac region tDS tDH tVAC DQS DQS Page 67 of 152 ...

Page 84: ... Rising Signal Falling Signal ΔTF ΔTR VREF DC VIL AC max ΔTF VIH AC min VREF DC ΔTR VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max nominal slew rate nominal slew rate VREF to ac region VREF to ac region DQS VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max VSS tDH tDS Note1 NOTE DQS signal must be monotonic between VIL AC max and VIH AC min Page 68 of 152 ...

Page 85: ... VSS Setup Slew Rate Setup Slew Rate Rising Signal Falling Signal ΔTF ΔTR tangent line VREF DC VIL AC max ΔTF tangent line VIH AC min VREF DC ΔTR VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max tangent tangent VREF to ac region VREF to ac region line line nominal line nominal line tDS tDH tDS tDH DQS DQS Page 69 of 152 ...

Page 86: ...TF ΔTR tangent line VREF DC VIL AC max ΔTF tangent line VIH AC min VREF DC ΔTR VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max tangent tangent VREF to ac region VREF to ac region line line nominal line nominal line tDS tDH DQS VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max VSS tDH tDS Note1 NOTE DQS signal must be monotonic between VIL DC max and VIH DC min Page 70 of 152 ...

Page 87: ...1 0 K4T51083QI K4T51043QI VSS Hold Slew Rate Hold Slew Rate Falling Signal Rising Signal ΔTR ΔTF VREF DC VIL DC max ΔTR VIH DC min VREF DC ΔTF VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max nominal slew rate nominal slew rate dc to VREF region dc to VREF region tDS tDH tDS tDH DQS DQS Page 71 of 152 ...

Page 88: ... Signal Rising Signal ΔTR ΔTF VREF DC VIL DC max ΔTR VIH DC min VREF DC ΔTF VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max nominal slew rate nominal slew rate dc to VREF region dc to VREF region tDS tDH DQS VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max VSS tDH tDS Note1 NOTE DQS signal must be monotonic between VIL DC max and VIH DC min Page 72 of 152 ...

Page 89: ...QI Hold Slew Rate ΔTF ΔTR tangent line VIH DC min VREF DC ΔTF tangent tangent dc to VREF region dc to VREF region line line nominal line nominal line Falling Signal Hold Slew Rate tangent line VREF DC VIL DC max ΔTR Rising Signal tDS tDH tDS tDH DQS DQS VSS VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max Page 73 of 152 ...

Page 90: ...t tangent dc to VREF region dc to VREF region line line nominal line nominal line Falling Signal Hold Slew Rate tangent line VREF DC VIL DC max ΔTR Rising Signal NOTE DQS signal must be monotonic between VIL DC max and VIH DC min tDS tDH DQS VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max VSS tDH tDS Note1 VSS VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max Page 74 of 152 ...

Page 91: ... 247 154 ps 1 3 5 179 89 209 119 239 149 ps 1 3 0 167 83 197 113 227 143 ps 1 2 5 150 75 180 105 210 135 ps 1 2 0 125 45 155 75 185 105 ps 1 1 5 83 21 113 51 143 81 ps 1 1 0 0 0 30 30 60 60 ps 1 0 9 11 14 19 16 49 46 ps 1 0 8 25 31 5 1 35 29 ps 1 0 7 43 54 13 24 17 6 ps 1 0 6 67 83 37 53 7 23 ps 1 0 5 110 125 80 95 50 65 ps 1 0 4 175 188 145 158 115 128 ps 1 0 3 285 292 255 262 225 232 ps 1 0 25 3...

Page 92: ...he nominal slewrate line between shaded dc to VREF DC region use nominal slew rate for derating value see Fig ure 17 If the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to VREF DC region the slew rate of a tangent line to the actual signal from the dc level to VREF DC level is used for derating value see Figure 18 Although for slow slew rates the total setup ...

Page 93: ...83QI K4T51043QI VSS Setup Slew Rate Setup Slew Rate Rising Signal Falling Signal ΔTF ΔTR VREF DC VIL AC max ΔTF VIH AC min VREF DC ΔTR VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max nominal slew rate nominal slew rate VREF to ac region VREF to ac region CK CK tIS tIH tIS tIH Page 77 of 152 ...

Page 94: ...p Slew Rate Setup Slew Rate Rising Signal Falling Signal ΔTF ΔTR tangent line VREF DC VIL AC max ΔTF tangent line VIH AC min VREF DC ΔTR tangent tangent VREF to ac region VREF to ac region line line nominal line nominal line CK CK tIS tIH tIS tIH VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max Page 78 of 152 ...

Page 95: ...083QI K4T51043QI Hold Slew Rate Hold Slew Rate Falling Signal Rising Signal ΔTR ΔTF VREF DC VIL DC max ΔTR VIH DC min VREF DC ΔTF nominal slew rate nominal slew rate dc to VREF region dc to VREF region CK CK tIS tIH tIS tIH VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max VSS Page 79 of 152 ...

Page 96: ...ew Rate ΔTF ΔTR tangent line VIH DC min VREF DC ΔTF tangent tangent dc to VREF region dc to VREF region line line nominal line nominal line Falling Signal Hold Slew Rate tangent line VREF DC VIL DC max ΔTR Rising Signal CK CK tIS tIH tIS tIH VDDQ VIH AC min VIH DC min VREF DC VIL DC max VIL AC max VSS Page 80 of 152 ...

Page 97: ...n on time max is when the ODT resis tance is fully on Both are measured from tAOND which is interpreted differently per speed bin For DDR2 400 533 tAOND is 10 ns 2 x 5 ns after the clock edge that registered a first ODT HIGH if tCK 5 ns For DDR2 667 800 tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges 17 ODT turn off time min is wh...

Page 98: ...from the differential data strobe crosspoint to the input sig nal crossing at the VIH DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL DC level for a rising signal applied to the device under test DQS DQS signals must be monotonic between VIL DC max and VIH DC min See Figure 20 22 Input waveform timing is referenced from the inp...

Page 99: ...t is these parameters should be met whether clock jitter is present or not 31 These parameters are measured from a data signal L U DM L U DQ0 L U DQ1 etc transition edge to its respective data strobe signal L U R DQS DQS crossing 32 For these parameters the DDR2 SDRAM device is characterized and verified to support tnPARAM RU tPARAM tCK avg which is in clock cycles assuming all input clock jitter ...

Page 100: ... per defines the single period jitter when the DLL is already locked tJIT per lck uses the same definition for single period jitter during the DLL locking period only tJIT per and tJIT per lck are not guaranteed through final production testing tJIT cc tJIT cc lck tJIT cc is defined as the difference in clock period between two consecutive clock cycles tJIT cc Max of tCKi 1 tCKi tJIT cc defines th...

Page 101: ... the measured jitter into a DDR2 667 SDRAM has tERR 6 10per min 272 ps and tERR 6 10per max 293 ps then tDQSCK min derated tDQSCKmin tERR 6 10per max 400 ps 293 ps 693 ps and tDQSCKmax derated tDQSCKmax tERR 6 10per min 400 ps 272 ps 672 ps Similarly tLZ DQ for DDR2 667 derates to tLZ DQ min derated 900 ps 293 ps 1193 ps and tLZ DQ max derated 450 ps 272 ps 722 ps 41 When the device is operated wi...

Page 102: ...th of 0 5 relative to tCK avg tAOFmin and tAOFmax should each be derated by the same amount as the actual amount of tCH avg offset present at the DRAM input with respect to 0 5 For example if an input clock has a worst case tCH avg of 0 48 the tAOFmin should be derated by subtracting 0 02 x tCK avg from it whereas if an input clock has a worst case tCH avg of 0 52 the tAOFmax should be derated by ...

Page 103: ...0MHz 15pF TTL Load which is equivalent to 100MHz Fast program time 1 4ms typ and 5ms max page 256 byte per page Byte program time 7us typical Continuously program mode automatically increase address under word program mode Fast erase time 60ms typ sector 4K byte per sector 0 7s typ block 64K byte per block 14s typ chip for 16Mb 25s typ for 32Mb and 50s typ for 64Mb Low Power Consumption Low active...

Page 104: ...rial Flash memory which is configured as 4 194 304 x 8 internally When it is in two I O read mode the structure becomes 16 772 216 bits x 2 The KH25L6405D are 67 108 864 bit serial Flash memory which is configured as 8 388 608 x 8 internally When it is in two I O read mode the structure becomes 33 554 432 bits x 2 please refer to the Two I O Read mode section TheKH25L1605D 3205D 6405Dfeatureaseria...

Page 105: ...dby mode and draws less than 20uA DC current The KH25L1605D 3205D 6405D utilizes MXIC s proprietary memory cell which reliably stores memory contents even after 100 000 program and erase cycles Read Performance KH25L1605D V V V 14 hex C2 14 hex if ADD 0 C2 14 hex if ADD 0 C2 20 15 hex Identifier Protection and Security Featu res Part Name Additional Device ID command EF hex RDID command 9F hex 512...

Page 106: ...without deselecting the device VCC 3 3V Power Supply GND Ground PIN DESCRIPTION 16 PIN SOP 300mil 8 LANDWSON 8x6mm 6x5mm forKH25Lxx05D 8 PIN SOP 200mil 150mil PACKAGE OPTIONS 16M 32M 64M 150mil8 SOP V 209mil8 SOP V V 300mil16 SOP V V V 300mil8 PDIP V V 6x5mmWSON V V 8x6mmWSON V 1 2 3 4 5 6 7 8 HOLD VCC NC NC NC NC CS SO SIO1 16 15 14 13 12 11 10 9 SCLK SI SIO0 NC NC NC NC GND WP ACC 1 2 3 4 CS SO ...

Page 107: ...LOCK DIAGRAM Address Generator Memory Array Page Buffer Y Decoder X Decoder Data Register SRAM Buffer SI SIO0 SCLK Clock Generator State Machine Mode Logic Sense Amplifier HV Generator Output Buffer SO SIO1 CS WP ACC HOLD Page 91 of 152 ...

Page 108: ... 4 6V or 0 5V for period up to 20ns 4 All input and output pins may overshoot to VCC 0 5V while VCC 0 5V is smaller than or equal to 4 6V RATING VALUE AmbientOperatingTemperature 0 C to 70 C for commercial grade StorageTemperature 55 Cto125 C Applied Input Voltage 0 5V to 4 6V Applied Output Voltage 0 5V to 4 6V VCC to Ground Potential 0 5V to 4 6V ABSOLUTEMAXIMUMRATINGS ELECTRICAL SPECIFICATIONS ...

Page 109: ...Level Input timing referance level Output timing referance level 0 8VCC 0 7VCC 0 3VCC 0 5VCC 0 2VCC Note Input pulse rise and fall time are 5ns DEVICE UNDER TEST DIODES IN3064 OR EQUIVALENT CL 6 2K ohm 2 7K ohm 3 3V CL 30pF Including jig capacitance CL 15pF Including jig capacitance for 86MHz and 50MHz 2x I O Page 93 of 152 ...

Page 110: ... Current PP CS VCC ICC3 VCC Write Status 20 mA Programstatusregisterinprogress Register WRSR CS VCC Current ICC4 VCC Sector Erase 1 20 mA Erase in Progress Current SE CS VCC ICC5 VCC Chip Erase 1 20 mA Erase in Progress Current CE CS VCC VHH Voltage for ACC Program 11 0 11 5 V VCC 2 7V 3 6V EraseAcceleration VIL Input Low Voltage 0 5 0 3VCC V VIH Input High Voltage 0 7VCC VCC 0 4 V VOL Output Low ...

Page 111: ...DH Data In Hold Time 5 ns tCHSH CS Active Hold Time relative to SCLK 5 ns tSHCH CS Not Active Setup Time relative to SCLK 5 ns tSHSL tCSH CS Deselect Time 100 ns tSHQZ 2 tDIS Output Disable Time 64Mb 2 7V 3 6V 10 ns 32Mb 3 0V 3 6V 8 ns 16Mb tCLQV tV Clock Low to Output Valid 64Mb 2 7V 3 6V 10 ns 32Mb 3 0V 3 6V 8 ns 16Mb tCLQX tHO Output Hold Time 0 ns tHLCH HOLD Setup Time relative to SCLK 5 ns tC...

Page 112: ...ycle Time 90 150 ms tBE Block Erase Cycle Time 0 7 2 s tCE Chip Erase Cycle Time 64Mb 50 80 s 32Mb 25 50 s 16Mb 14 30 s Notes 1 tCH tCL must be greater than or equal to 1 fC 2 Value guaranteed by characterization not 100 tested in production 3 Expressed as a slew rate 4 Only applicable as a constraint for a WRSR instruction when SRWD is set at 1 5 Test condition is shown as Figure 5 Page 96 of 152...

Page 113: ...1 10 ms VWI 1 Write Inhibit Voltage 1 5 2 5 V INITIAL DELIVERY STATE The device is delivered with the memory array erased all bits are set to 1 each byte contains FFh The Status Register contains 00h all Status Register bits are 0 Note 1 These parameters are characterized only Table 11 Power Up Timing and VWI Threshold Page 97 of 152 ...

Page 114: ...5D Figure 8 Serial Input Timing SCLK SI CS MSB SO tDVCH High Z LSB tSLCH tCHDX tCHCL tCLCH tSHCH tSHSL tCHSH tCHSL Figure 9 Output Timing LSB ADDR LSB IN tSHQZ tCH tCL tQLQH tQHQL tCLQX tCLQV tCLQX tCLQV SCLK SO CS SI Page 98 of 152 ...

Page 115: ...ing tCHHL tHLCH tHHCH tCHHH tHHQX tHLQZ SCLK SO CS HOLD SI is don t care during HOLD operation Figure 11 WP Disable Setup and Hold Timing during WRSR when SRWD 1 High Z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tWHSL tSHWL SCLK SI CS WP SO Page 99 of 152 ...

Page 116: ...14 Read Identification RDID Sequence Command 9F 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 Command 0 Manufacturer Identification High Z MSB 15 14 13 3 2 1 0 Device Identification MSB 7 6 5 3 2 1 0 16 17 18 28 29 30 31 SCLK SI CS SO 9F 2 1 3 4 5 6 7 High Z 0 06 Command SCLK SI CS SO 2 1 3 4 5 6 7 High Z 0 04 Command SCLK SI CS SO Page 100 of 152 ...

Page 117: ...12 13 14 15 command 0 7 6 5 4 3 2 1 0 Status Register Out High Z MSB 7 6 5 4 3 2 1 0 Status Register Out MSB 7 SCLK SI CS SO 05 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 Status Register In 0 7 6 5 4 3 2 0 1 MSB SCLK SI CS SO 01 High Z command SCLK SI CS SO 23 2 1 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 22 21 3 2 1 0 36 37 38 7 6 5 4 3 1 7 0 Data Out 1 24 Bit Address 0 MSB MSB 2 39 Data Out 2 03 High Z ...

Page 118: ... Command 0B 23 2 1 3 4 5 6 7 8 9 10 28 29 30 31 22 21 3 2 1 0 High Z 24 BIT ADDRESS 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 7 6 5 4 3 2 0 1 DATA OUT 1 Dummy Byte MSB 7 6 5 4 3 2 1 0 DATA OUT 2 MSB MSB 7 47 7 6 5 4 3 2 0 1 35 SCLK SI CS SO SCLK SI CS SO 0B Command Page 102 of 152 ...

Page 119: ...it7 bit5 address bit23 bit21 bit19 bit1 21 22 23 24 25 26 27 Figure 20 Page Program PP Sequence Command 02 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 23 2 1 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 22 21 3 2 1 0 36 37 38 24 Bit Address 0 7 6 5 4 3 2 0 1 Data Byte 1 39 51 7 6 5 4 3 2 0 1 Data Byte 2 7 6 5 4 3 2 0 1 Data Byte 3 Data Byte 256 2079 2078 2077 2076 2075 2074 2073 7 6 5 4 3 2 0 1 2072 ...

Page 120: ...turn the SO pin to tri state 3 ToendtheCPmode eitherreachingthehighestunprotectedaddressorsendingWriteDisable WRDI command 04hex mayachieveitandthenitisrecommendedtosendRDSRcommand 05hex toverifyifCPmodeisended Note SE command is 20 hex Note BE command is D8 hex 24 Bit Address 2 1 3 4 5 6 7 8 9 29 30 31 0 23 22 2 0 1 MSB SCLK CS SI D8 Command CS SCLK 0 1 6 7 8 9 SI Command AD hex 30 31 31 S0 high ...

Page 121: ...ES Sequence Command AB Note CE command is 60 hex or C7 hex 2 1 3 4 5 6 7 0 60 or C7 SCLK SI CS Command 2 1 3 4 5 6 7 0 tDP Deep Power down Mode Stand by Mode SCLK CS SI B9 Command 23 2 1 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 22 21 3 2 1 0 36 37 38 7 6 5 4 3 2 0 1 High Z Electronic Signature Out 3 Dummy Bytes 0 MSB Stand by Mode Deep Power down Mode MSB tRES2 SCLK CS SI SO AB Command Page 105 of...

Page 122: ...ure 28 Read Electronic Manufacturer Device ID REMS Sequence Command 90 or EF 15 14 13 3 2 1 0 2 1 3 4 5 6 7 8 9 10 2 Dummy Bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 7 6 5 4 3 2 0 1 Manufacturer ID ADD 1 MSB 7 6 5 4 3 2 1 0 Device ID MSB MSB 7 47 7 6 5 4 3 2 0 1 35 31 30 29 28 SCLK SI CS SO SCLK SI CS SO X 90 High Z Command 2 1 3 4 5 6 7 0 tRES1 Stand by Mode Deep Power down Mode High Z SCL...

Page 123: ...Timing VCC VCC min VWI Reset State of the Flash Chip Selection is Not Allowed Program Erase and Write Commands are Ignored tVSL tPUW time Read Command is allowed Device is fully accessible VCC max Note VCC max is 3 6V and VCC min is 2 7V Page 107 of 152 ...

Page 124: ...ed the device may not operate correctly Figure A AC Timing at Device Power Up Notes 1 Sampled not 100 tested 2 For AC spec tCHSL tSLCH tDVCH tCHDX tSHSL tCHSH tSHCH tCHCL tCLCH in the figure please refer to AC CHARACTERISTICS table Symbol Parameter Notes Min Max Unit tVR VCC Rise Time 1 0 5 500000 us V SCLK SI CS VCC MSB IN SO tDVCH High Impedance LSB IN tSLCH tCHDX tCHCL tCLCH tSHCH tSHSL tCHSH t...

Page 125: ... 1 4 5 ms Erase ProgramCycle 100 000 cycles Note 1 Typical program and erase time assumes the following conditions 25 C 3 3V and checker board pattern 2 Under worst conditions of 70 C and 2 7V 3 System level overhead is the time required to execute the first bus cycle sequence for the programming command MIN MAX Input Voltage with respect to GND on ACC 1 0V 11 5V Input Voltage with respect to GND ...

Page 126: ...from 47MHz to 862MHz The MAX3543 includes a variable gain low noise input amplifier an RF tracking filter image rejection mixer a power detector optional RF gain control loop RFAGC VCO with fractional N PLL IF band pass anti alias filter IF variable gain amplifier separate analog and digital IF outputs including digital SAW bandwidth switch and a crystal oscillator 0 1 2 0 33 45 67 8 5 1 8 59 8 4 ...

Page 127: ... Output Logic Level Low 3 mA sink current 0 4 V TEST 11 Output Logic Level High Vcc 0 5 V TEST 12 Maximum Clock Rate 400 kHz TEST Typical Operating Circuit as shown RF Center Frequency 666MHz IF Center Frequency 36 15MHz Registers set according to Table 1 Fref 16 MHz RFVGC IFVGC VCC 3 3V TA 25º unless otherwise noted 0 0 1 21a RFINL Operating Frequency Range Noise Figure specification is met over ...

Page 128: ...00 9 5dB Vpp to Vrms modulated waveform 46 dBm 0 2 3 76 RF N Divider Integer Part 19 251 77 Fractional N Resolution 20 Bits 78a Phase Detector Frequency FREF 2 8 10 5 MHz 78b Phase Detector Frequency FREF 1 16 21 MHz 80 Frequency 16 21 MHz 83 External Overdrive Level AC coupled sine wave input 0 5 Vpp 85 Output Freq 1 4 modes 4 4 Fxtal MHz 86 Output Level Load 20kM 3pF 750 mVpp Page 112 of 152 ...

Page 129: ...GA Output Connect to the demodulator input Requires DC blocking capacitors 17 GNDDIG Digital Ground 18 REFOUT Crystal Output for demodulator Output frequency is XTAL 1 or 4 19 VCCDIG Digital supply 20 SCL 2 Wire Serial Clock Interface Requires a pullup resistor to VCC 21 XTALB Crystal Oscillator Base pin Connect to crystal through a DC blocking cap and connect a cap to XTALE 22 XTALE Crystal Oscil...

Page 130: ... frequency This along with small SOT 23 TSOT 23 footprint provides small PCB area application Applications Portable Navigation Device Smart phone USB Dongle Set Top Box Media Player Features low Rds on for internal switches top bottom ο SY8008A 300m 250m 0 6A ο SY8008B 250m 200m 1A ο SY8008C 200m 150m 1 2A 2 5 5 5V input voltage range 1 5MHz switching frequency minimizes the external components In...

Page 131: ... Connect this pin to the center point of the output resistor divider as shown in Figure 1 to program the output voltage Vout 0 6 1 R1 R2 Add optional C1 10p 47pF to speed up transient response Absolute Maximum Ratings Note 1 Supply Input Voltage 6 0V Enable FB Voltage VIN 0 6V Power Dissipation PD TA 25 C SOT23 5 TSOT23 5 0 4W Package Thermal Resistance Note 2 SOT23 5 TSOT23 5 θJA 250 C W SOT23 5 ...

Page 132: ...quency FOSC IOUT 100mA 1 5 MHz Min ON Time 50 ns Max Duty Cycle 100 Thermal Shutdown Temperature TSD 160 C Note 1 Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device These are for stress ratings Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposu...

Page 133: ...0 0 30 0 50 2 80 3 10 2 70 3 00 1 50 1 70 0 30 0 50 2 80 3 10 2 70 3 00 Recommended Pad Layout 0 1 0 15 0 25 REF 0 3 0 6 0 1 0 15 0 25 REF 0 3 0 6 1 0 1 3 0 01 0 1 1 90 TYP 0 95 TYP 1 0 1 3 0 01 0 1 1 90 TYP 0 95 TYP Notes All dimensions are in millimeters All dimensions don t include mold flash metal burr Page 117 of 152 ...

Page 134: ... 40 0 80 0 55 0 95 TYP 1 50 1 70 0 30 0 50 2 80 3 10 2 70 3 00 1 50 1 70 0 30 0 50 2 80 3 10 2 70 3 00 Recommended Pad Layout 0 3 0 6 0 1 0 20 0 25 REF 1 00 max 0 01 0 1 1 90 TYP 0 95 TYP Notes All dimensions are in millimeters All dimensions don t include mold flash metal burr Page 118 of 152 ...

Page 135: ...requency Ordering Information SY8009 Temperature Code C 40 C 85 C Package Code AA SOT23 5 EB SSOT23 6 Spec Code Features low Rds on for internal switches top bottom SY8009A 200mohm 150mohm 1 5A SOT23 5 SY8009B 150mohm 120mohm 2 0A SSOT23 6 3 5 5V input voltage range High switching frequency minimizes the external components SY8009A 1 5MHz SY8009B 1MHz Internal softstart limits the inrush current 1...

Page 136: ...Feedback Pin Connect this pin to the center point of the output resistor divider as shown in Figure 1 to program the output voltage Vout 0 6 1 R1 R2 Absolute Maximum Ratings Note 1 Supply Input Voltage 6 0V Enable FB Voltage VIN 0 6V Power Dissipation PD TA 25 C SOT23 5 SSOT23 6 0 4W Package Thermal Resistance Note 2 SOT23 5 SSOT23 6 θJA 250 C W SOT23 5 SSOT23 6 θJC 130 C W Junction Temperature Ra...

Page 137: ...or Frequency FOSC IOUT 500mA SY8009B 1 MHz Min ON Time 50 ns Max Duty Cycle 100 Thermal Shutdown Temperature TSD 160 C Note 1 Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device These are for stress ratings Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not im...

Page 138: ...30 0 50 2 80 3 10 2 70 3 00 1 50 1 70 0 30 0 50 2 80 3 10 2 70 3 00 Recommended Pad Layout 0 1 0 15 0 25 REF 0 3 0 6 0 1 0 15 0 25 REF 0 3 0 6 1 0 1 3 0 01 0 1 1 90 TYP 0 95 TYP 1 0 1 3 0 01 0 1 1 90 TYP 0 95 TYP Notes All dimensions are in millimeters All dimensions don t include mold flash metal burr Page 122 of 152 ...

Page 139: ...0 1 90 0 60 1 00 2 30 2 50 2 50 3 00 0 25 0 40 Recommended Pad Layout 0 30 0 60 0 10 0 20 0 30 0 60 0 10 0 20 2 95 3 10 0 90 1 00 0 01 0 10 0 95 TYP 2 95 3 10 0 90 1 00 0 01 0 10 0 95 TYP Notes All dimensions are in millimeters All dimensions don t include mold flash metal burr Page 123 of 152 ...

Page 140: ...t voltage ripple and small external inductor and capacitor sizes are achieved with 400 kHz switching frequency Applications Set Top Box Portable TV Access Point Router DSL Modem LCD TV Features low Rds on for internal switches top bottom 150 100 mΩ 4 15V input voltage range 400 kHz switching frequency Internal softstart limits the inrush current 2 0 6V reference 100 dropout operation RoHS Complian...

Page 141: ...gram the output voltage Vout 0 6 1 R1 R2 EN 8 Enable control Pull high to turn on Do not float NC 2 3 No connection Absolute Maximum Ratings Note 1 Supply Input Voltage 16V Enable FB Voltage VIN 0 6V Power Dissipation PD TA 25 C SO8 0 65W Package Thermal Resistance Note 2 θJA 90 C W θJC 45 C W Junction Temperature Range 150 C Lead Temperature Soldering 10 sec 260 C Storage Temperature Range 65 C t...

Page 142: ... 4 MHz Min ON Time 50 ns Max Duty Cycle 90 Thermal Shutdown Temperature TSD 160 C Note 1 Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device These are for stress ratings Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum ra...

Page 143: ... 0 50 5 80 6 10 3 80 4 00 Recommended Pad Layout 4 5 0 25 base 0 8 0 18 0 25 0 25 0 50 0 60 0 85 4 5 0 25 base 0 8 0 18 0 25 0 25 0 50 0 60 0 85 1 27 TYP 1 40 1 60 0 08 0 25 4 80 5 00 1 27 TYP 1 40 1 60 0 08 0 25 4 80 5 00 Notes All dimensions are in millimeters All dimensions don t include mold flash metal burr Page 127 of 152 ...

Page 144: ...put voltage ripple and small external inductor and capacitor sizes are achieved with 400KHz switching frequency Applications Set Top Box Portable TV Access Point Router DSL Modem LCD TV Features low Rds on for internal switches top bottom 120 80 m 4 15V input voltage range 400KHz switching frequency Internal softstart limits the inrush current 2 0 6V reference RoHS Compliant and Halogen Free Compa...

Page 145: ...r divider as shown in Figure 1 to program the output voltage Vout 0 6 1 R1 R2 EN 8 Enable control Pull high to turn on Do not float NC 2 3 No connection Absolute Maximum Ratings Note 1 Supply Input Voltage 16V Enable FB Voltage VIN 0 6V Power Dissipation PD TA 25 C SO8E 1 2W Package Thermal Resistance Note 2 θJA 50 C W θJC 10 C W Junction Temperature Range 150 C Lead Temperature Soldering 10 sec 2...

Page 146: ...M Hz Min ON Time 50 ns Max Duty Cycle 90 Thermal Shutdown Temperature TSD 160 C Note 1 Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device These are for stress ratings Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rati...

Page 147: ... 80 6 10 3 80 4 00 Recommended Pad Layout 4 5 0 25 base 0 8 0 18 0 25 0 25 0 50 0 60 0 85 4 5 0 25 base 0 8 0 18 0 25 0 25 0 50 0 60 0 85 1 27 TYP 1 40 1 60 0 08 0 25 4 80 5 00 1 27 TYP 1 40 1 60 0 08 0 25 4 80 5 00 Notes All dimensions are in millimeters All dimensions don t include mold flash metal burr Page 131 of 152 ...

Page 148: ...PCB INFORMATION PCB of main board 1 Page 132 of 152 ...

Page 149: ...PCB of main board 2 Page 133 of 152 ...

Page 150: ...PCB of main board 3 Page 134 of 152 ...

Page 151: ...PCB of main board 4 Page 135 of 152 ...

Page 152: ...PCB of main board 5 Page 136 of 152 ...

Page 153: ...PCB of main board 6 Page 137 of 152 ...

Page 154: ...PCB of DVD 1 Page 138 of 152 ...

Page 155: ...PCB of DVD 2 Page 139 of 152 ...

Page 156: ...PCB of DVD 3 Page 140 of 152 ...

Page 157: ...PCB of DVD 4 Page 141 of 152 ...

Page 158: ...PCB of DVD 5 Page 142 of 152 ...

Page 159: ...PCB of DVD 6 Page 143 of 152 ...

Page 160: ...1 USB port STEP1 cope correct file to usb disk the file must named as MERGE bin STEP2 plug usb disk into usb port on board and ensure it is stable STEP3 open the factory menu MENU 4321 or SOURCE 2580 as PIC1 PIC1 STEP4 select the item Software Update USB to open update menu as PIC2 PIC2 STEP5 press left key to start update STEP6 TV will standby if finish update Update processing as PIC3 Page 144 o...

Page 161: ...IC3 2 ISP connect on board usb update tool is used on this method the tool as PIC4 of course update SW is used together it as PIC5 图 4 PIC5 STEP1 ensure usb tool connect correctly As PIC6 Page 145 of 152 ...

Page 162: ...the blue 4pin connector it is correct ISP connector STEP2 run the update SW and press connect button you shall see the picture like PIC7 PIC7 PIC8 If picture looks like PIC8 please double check stpe1 and do step2 again STEP3 press Read button then select the correct update file Page 146 of 152 ...

Page 163: ...ers as PIC9 then press Run PIC9 STEP5 please kindly wait a moment it is finish as PIC10 PIC10 3 VGA PORT You need a adapter looks like PIC11 PIC11 Please ensure connect correctly with the VGA adapter then do like ISP update steps Page 147 of 152 ...

Page 164: ...gineer or saler file as PIC12 STEP1 plug USB TOOL into usb port of your computer the computer will auto check new HW and lead you to setup driver PIC12 STEP2 there are three drivers you should setup NOTE usb drivers and update SW just be operated on windows XP OS Page 148 of 152 ...

Page 165: ...b The pattern for VGA ADC must include pure white 100IRE and pure black 0IRE VGA checkerboard pattern R G B range 0 255 2 AGING MODE TV manufactory would do the aging mode experiment for the new product When entering aging mode the machine will go to remember state It will quit when turning to OFF 3 REGION 1 COUNTRY If we change country then OSD Language Audio Language Subtitle Language LCN and Ti...

Page 166: ...st the contrast and brightness Generally we fix the G value just change the R and B to a proper value The brightness of testing region must be upon 1 NIT and under 80 of the max value 7 PICTURE MODE There are contrast brightness color sharpness and tint in this page 8 SPECIAL SET 1 2HOUR OFF The TV only run 2 hours when turn on every time After 2 hours it will turn off automatically 2 WDT Watch Do...

Page 167: ...off for designer default is off when turn on can write or read register value by debug tool 12 OverScan For the OEM factory adjust the imagine valid size by theirself as what they want And they tell the designer the value to write it into the SW 13 BMTEST For the designer use when one board change the DDR chip has to do the phase test 9 SW INFORMATION This item records the time when the SW built 1...

Page 168: ...work 7 HOTEL ATV PRO When the POWER ON SOURCE is set to ATV the TV will go to the selected ATV program when power on 8 HOTEL DTV PRO When the POWER ON SOURCE is set to DTV the TV will go to the selected DTV program when power on 9 HOTEL POWER VOL We can set the default volume when power on 11 POWER ON Go to power on state mode when AC on OFF Go to standby state when AC on LAST Go to last state tha...

Page 169: ...ssis 8 Ultra Slim Ultra slim LED panel slim chassis Cabinet design modification No 0 Glass 9key Glass 3key 1 Glass 3key 3 Glass smile 9key 5 Glass smile 3keys 7 Glass smile line 9keys 9 Glass smile line 3keys 4 Plastic 9key 6 Plastic 3key Front cabinet material G Glass Glass P Plastic M Metal Front cabinet color B Black Black S Silver W White R Red Front cabinet surface finishing G Glossy Glossy M...

Page 170: ...RT 1xSCART A1 1xSCART A2 2xSCART Specific for markets E European Simbol veiling will mean E British B British R Russian Presence of MHEG5 decoder 5 MHEG 5 MHEG 5 No MHEG 5 Comment Comment please use Value selection column settings to change TV model options and get interactive demonstration of its influence to the TV model name Just click on the value clik on the pop up symbol and select new one f...

Page 171: ...ing box color El dalys Tiekimas Front cab Finishing Glossy Box sticker for TV color Panelės Tiekimas Stand design rectangle stand pivot Security bar code label Mech dalys Tiekimas Stand material Plastic Brand name label Tara Tiekimas Stand color Black Info label Spausdiniai Tiekimas Stand surf finishing Glossy TV serial No Gamyba Gamyba TV specification Bar code No Marketingo vadybininko pastabos ...

Page 172: ...Confidential 18 08 2021 Page 4 Page 4 TV PO sheet Assembly level CBU Required SKD content Full SKD tuner separate Required CKD content SMPS contol board ...

Page 173: ...ot defined 26 50Hz 26 HD Not defined 26L 50Hz 26 HD Not defined 26FL 50Hz 26 HD Not defined C26FL 100Hz 26 FHD Not defined 32F 50Hz 32 HD Not defined C32F 100Hz 32 FHD Not defined 32L 50Hz 32 HD Not defined C32L 100Hz 32 HD Not defined 32FL 50Hz 32 FHD Not defined C32FL 100Hz 32 FHD LC370WXN SCA1 37 50Hz 37 HD Not defined 40FL 50Hz 40 FHD Not defined C40FL 100Hz 40 HD Not defined 42 50Hz 42 HD Not...

Page 174: ...CCFL CCFL CCFL LED CCFL CCFL CCFL CCFL LED LED CCFL CCFL LED CCFL LED LED LED CCFL CCFL LED LED LED LED CCFL LED LED CCFL CCFL CCFL CCFL LED LED CCFL Back Light LED CCFL ...

Page 175: ...aker cable and ferrite core subassembly 2 54mm 4pin pcs 0 26 OSCB001 2T604405501 1 25 to 2 0 6pin cable 550mm pcs 0 27 OSCB002 2T604505501 1 25 to 2 0 9pin cable 550mm pcs 0 28 BKCB001 2T601904001 Power inverter cable pcs 0 29 BKCB002 2T601114001 Inverter cable and ferrite core subassembly 2 0mm 8 to 6pin 400mm pcs 0 30 BKCB004 2T609102001 Power cable and ferrite core subassembly 2 0mm 8 to 8pin 2...

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