Shiratech Solutions Spark-100, Integration Manual, Page: 6 / 41

6 | Spark-100 HW user manual v1.3
2 Spark-100 Integration guide
The HW integration guide covers all the hardware issues related to how to connect the SoM to the
target device starting from power connectivity, connector details, pin-out options, description of the
various interfaces along with a reference design for most of the interfaces. By using the same design as
the reference board you can shorten the BSP development phase and reduce the risk of mistakes. The
reference design is based on the CB-50.
2.1 Power considerations
The Spark-100 uses a single 5V power input from which all the other required voltages are taken.?. The
Inlet power should be

Rise time: <= 3ms

Input voltage range: 5V +/- 5%
2.1.1 VCCBAT - FPGA Encryption Key power
The Altera SOC has an option to maintain an encryption key for FPGA configuration even if the system
power is down. For that pin S147 of the SMARC interface should be connected to a power source
(between 1.2V - 3V). If the option is not used connect pin S147 to 2.5V. The interface is connected to
VCCBAT(D7) pin of the SOC.
2.1.2 Spark Power scheme
The SPARK-100 has flexible power architecture to support the ARM core and the FPGA's power
requirements. The following figure describes the power architecture:
1.1V, 4A
Core
1.5V, 4A
DDR3
2.5V
1A
3.3V
0.6A
1.8V
0.6A
Programmable VCCPD
2.5V, 3.3V 0.6A
Vin 5V
HPS Core
FPGA VCC
HPS DDR3
FPGA I/O
FPGA PLL, OSC, I/O
Peripherals
FPGA I/O
Peripherals
Peripherals
FPGA I/O
FPGA VCCPD
Bank 3B, 4A
FPGA I/O
Bank 3B
FPGA I/O
Bank 4A
Programmable VCCIO
1.8V, 2.5V, 3.3V 0.6A
Programmable VCCIO
1.8V, 2.5V, 3.3V 0.6A
PG