Shiratech Solutions Spark-100, Integration Manual, Page: 19 / 41

19 | Spark-100 HW user manual v1.3
2.4 Clocks scheme
The SPARK-100 supports two clock schemes Basic – available when SOC SE devices are assembled or
Advanced – available when SOC SX devices are assembled.
2.4.1 Basic clock architecture – SE SOC devices
This option is provided for SE devices. In that case an internal 25 MHz clock is used for driving the HPS
clock inputs, it also provides two clock sources for the FPGA. These clocks are connected to CLK1P_V12
(pin V12 of the SOC) and to CLK0P (pin V11 of the SOC).
If additional clocks are required for the FPGA, they can be provided via the SMARC interface directly to
the FPGA.
2.4.2 Advance clock Configuration – SX SOC assembly only
For applications that require enhanced clocking mechanism, the Spark offers an additional clock
distributor device. The additional device used is CDCM6208 by TI, offering:

Low Noise Synthesizer (265 fs-rms Typical < 1 ppm Frequency Error and Eliminates Jitter) or Low
Noise Jitter Cleaner (1.6 pSec - need for Crystal Oscillators and Other rms Typical Jitter).

Any frequency using FPLL up to 800 MHz.

Support single ended or differential output.

Support several voltage levels, including a mix of levels.

4x Integer Down-divided Differential Clock.

4x Fractional or Integer Divided Differential.
The following figure describes the clock architecture:
Figure 12 – Spark – clock scheme
Fan Out
Buffer
HPS CLK1
HPS CLK2
FPGA CLK1
FPGA
CLKIN1
High Speed
Single PLL
Clock
Generator
CLKIN2
Bank
A
Bank
B
SMARC CONNECTOR
HPS
FPGA CLK2
CLKI0_p
CLKI1_p
CLKI0_n/p
CLKI1_n/p
CLKI2_n/p
CLKI4_n/p
Transceiver CLKI
Transceiver CLKI
Single ended 25 MHz
4 x Differential or 8 x Single ended
Any Frequency / Any Voltage
100, 125, 150 MHz Differential
100, 125, 150 MHz Differential
Any Clock Differential
25 MHZ
Local OSC
25 MHZ
C
L
K
I3
_
n
/p
CLK
CLK
C
L
K
I5
_
n
/p
C
L
K
I6
_
n
/p
C
L
K
I7
_
n
/p
Basic Clock
High End Clock
Any Clock
Differential or
Single Ended
Same Pin