Sharp Illustration XL-HP535E, Service Manual

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XL-HP535H/HP535E
8 – 1
Audio XL-HP535H/HP535E Service Manual XLHP535H Market E CHAPTER 8.
OTHERS
[1] FUNCTION TABLE OF IC
IC1 VHiLC78648E-1: CD Digital Signal Processor (LC78648E) (1/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No. Terminal Name Input/Output Setting in Reset Function
1 AVDD1 Output — Analog power supply pin 1.
2 SLCO Output —
slice level con-
trol.
Slice level Control output pin.
3 EFMIN Input — RF signal input pin.
4 RF Output — RF signal Output pin.
5 LPF Output — RF signal DC level detection LPF capacitor connection pin.
6 JITTC Input — Jitter detection capacitor connection pin.
7 AIN Input — A signal input pin.
8 CIN Input — C signal input pin.
9 BIN Input — B signal input pin.
10 DIN Input — D signal input pin.
11 FEC Output FE signal LPF capacitor connection pin.
12* PHLPF/RFMON Output ZHI Reference supply setting terminal.
13 VREF Output AVDD1/2 VREF voltage output pin.
14 EIN Input — E signal input pin.
15 FIN Input F signal input pin.
16 TEC Output TE signal LPF capacitor connection pin.
17 TE Output — TE signal output pin.
18 TEIN Input — TES signal generation TE signal input pin
19 LDD Output — Laser power control signal output pin.
20 LDS Input — Laser power control signal input pin.
21 FDO Output ADAVDD/2 Focus control output pin. D/A output.
22 TDO Output ADAVDD/2 Tracking control output pin. D/A output.
23 SLDO Output ADAVDD/2 Thread control output pin. D/A output.
24 SPDO Output ADAVDD/2 Spindle control output pin. D/A output.
25 AVSS2 — — Analog GND pin 2. Must always be connected to 0V.
26 AVDD2 — — Analog power supply pin 2.
27 DVDD — — Digital power supply pin.
28* DVSS — — Digital GND pin 2. Must always be connected to 0V.
29* VPB Output H Rough servo/phase control automatic switching monitor output pin.“H” for rough
servo and “L” for phase servo.
30* DEFECT Output L Defect signal output pin.
31* FSEQ Output L Synchronization signal detection output pin.
Outputs a high level when the Synchronization signal detection from the EFM sig-
nal and the internally generated Synchronization signal agree.
32* EFLG Output L C1, C2 error correction monitor pin
33* FSX Output L 7.35kHz Synchronization signal output pin.
CLV playback mode.
34 CONT1 Input/Output Input General pur-
pose I/O pin 1. Controlled by command from the microprocessor. Any of these
that are unused must be either set up as input pin ports and
connected to 0V, or set up as output pin ports and left open.
35 CONT2 Input/Output Input General pur-
pose I/O pin 2.
36 CONT3 Input/Output Input General pur-
pose I/O pin 3.
37* MONI1 Input/Output Input External deiemphasis setting pin, INternal signal monitor pin 1.Controlled by
microprocessor.
38* MONI2 Output L Internal signal monitor pin 2.
39* DOUT Output L Digital OUT output Pin. (EIAJ format)
40 TEST Input L Test input pin. Must always be connected to 0V.
41 LVDD — —
Left channel
D/A converter
L channel Power supply pin.
42 LCHO Output LVDD/2 L channel output supply pin.
43 LRVSS — — LR channel GND pin. Must always be connected to 0V.