FO-5700U
5 – 19
M65761FP (IC23) Terminal descriptions
I/F
Signal
Terminal No
I/O
Function
name
Host bus I/F
RESET*
68
I
H/W reset signal.
(29 pin)
CS*
62
I
Chip select signal.
A0-3
64,65,66,67
I
Address select signal of inner register.
BHE*
63
I
Access signal of upward byte (D8-15).
WR*
58
I
Write strobe signal.
RD*
57
I
Read strobe signal.
D0-15
71~74,
IO
Input/output data signal.
77~80,
(Use D0-7 when 8 bit bus)
83~86,
89~92
DMARQ
54
O
DMA request signal of encode data.
DMAAK*
56
I
DMA acknowledge signal of encode data.
INTR
53
O
Interrupt request signal.
BUS16
55
I
8 bit bus (D0-7) and 16 bit bus (D0-15) function select line.
Image data I/F
PD0-31
2~12
IO
Parallel image input/output bus.
Parallel
15~25
(Use PD0-15 when 16 bit bus)
28~37
PDRQ
38
O
DMA request signal of image data.
PDAK*
43
I
DMA acknowledge signal of image data.
PDRD*
41
I
Read strobe signal of image data.
PDWR*
42
I
Write strobe signal of image data.
Image data I/F
PRDY*
45
O
1 line input/output start ready signal of image data.
Serial
PTIM*
47
I
1 line transfer section signal of image data.
PXCK*
48
I
Transfer clock signal of image data.
PXCKO*
95
O
Transfer synchronization clock signal of image data.
SVID*
46
I
Input signal of image data.
RVID*
44
O
Output signal of image data.
Context I/F
CX0-11
2~12,15
I
Context input. (CX0 is possible to feed back in LSI)
(=PD0-11)
PEUPE*
19
I
Updata enable of RAM for PE. (Learning function ON/OFF)
(=PD15)
SPIX*
46
I
Encode image data input signal.
(=SVID*)
RPIX*
44
O
Decode image data output signal.
(=RVID*)
XCLK*
52
O
Context data transfer clock signal.
XWAIT*
49
I
Context data transfer wait signal.
XRDY*
45
O
Context data 1 stripe input/output start ready signal.
(=PRDY*)
XTIM*
47
I
Context data 1 stripe transfer section signal.
(=PTIM*)
Others
MCLK
61
I
Master clock input signal.
TEST0-1
98,99
I
Signal for test. (Usually connect to GND)
VCC/GND
1,13,14,26,27,
–
Power(+5V)/Ground.
39,40,50,51,59,
60,69,70,75,76,
81,82,87,88,93,
94,100
Note : Most of context IF signal line is shared with image data I/F signal line.
It is shown that * of the signal name is negative logic.
[2-1] Circuit description of memory PWB
It is composed by the flash memory of 2Mbyte, and attached to the
CNOP connecter of the control PWB circuit. It can be expanded by sub-
stituting FO-3MK(OPTION) for the standard memory PWB to 5MB.
1) LH28F016SUT(IC4) ... pin-56, TSOP
(16 Mbit flash memory)
This memory is a nonvolatile type whose content does not volatilize
even if power is turned off, and stores the copied, sent and received
image data. Moreover, the initially registerd data, registered content of
“RELAY” key and registered content of “CONF” key are stored.
2) W24010S-70L(IC21, IC36) ... pin-32, SOP
(1 Mbit SRAM)
The setting of receiving mode, optional setting content, soft switch con-
tent and daily data are stored. Even if the power supply of the main body
is turned off, it is backed up with a lithium battery.
Summary of Contents for FO-5700
Page 83: ...FO 5700U LIU PWB parts layout 6 20 ...
Page 86: ...FO 5700U Printer PWB parts layout Top side 6 23 ...
Page 87: ...FO 5700U Printer PWB parts layout Bottom side 6 24 ...
Page 89: ...FO 5700U Power supply PWB parts layout 6 26 ...
Page 100: ...FO 5700U 6 37 Memory PWB parts layout Top side Memory PWB parts layout Bottom side ...