16
DV-HR300U
FLOW CHART No.2
Drive is not working properly (communication failure with IC7506).
Is
A
T
API reset released? (CN4501 pin 1 R4537: "H" level)
NO
Check IC7506 and peripheral
circuits.
YES
YES
Check following items.
NO
Check power unit and PC_12V
and PC_5V circuits.
Communicating with drive via
A
T
API?
Access drive when CN4501 pin 37 CS0 and pin 38 CS1 are at "L"
level. (Communication is ongoing if intermittently set at LOW
.)
CN4501 pin 35 DA0, pin 33 DA1, pin 36 DA2 and
A
T
API register
address (Intermittently set at LOW).
CN4501 pin 31 INTRQ is at "H" level when drive interrupts. Output
after processing transfer command from IC7506, etc.
CN4501 pin 21 DMARQ is at "L" level when drive requests data
transfer
.
CN4501 pin 29 DMACK is at "L" level when IC7506 receives data
transfer for DMARQ from drive.
When CN4501 pin 25 DIOR and pin 23 DIOW are at "L" level,
IC7506 sends REASD/WRITE to drive. (Communication is ongoing
if CS and DA
are intermittently set at LOW
.)
Are 12V and 5V applied to drive?
FLOW CHART No.3
HDD is not working properly (communication failure with IC7506).
Is
A
T
API reset released? (CN4502 pin 40 R4566: "H" level)
NO
Check IC7506 and peripheral
circuits.
YES
YES
Check following items.
NO
Check power unit and PC_12V
and PC_5V circuits.
Communicating with drive via
A
T
API?
Access drive when CN4502 pin 4 CS0 and pin 3 CS1 are at "L"
level. (Communication is ongoing if intermittently set at LOW
.)
CN4502 pin 6 DA0, pin 8 DA1, pin 5 DA2 and
A
T
API register
address (intermittently set at LOW).
CN4502 pin 10 INTRQ is at "H" level when drive interrupts. Output
after processing transfer command from IC7506, etc.
CN4502 pin 20 DMARQ is at "L" level when drive requests data
transfer
.
CN4502 pin 12 DMACK is at "L" level when IC7506 receives data
transfer for DMARQ from drive.
When CN4502 pin 16 DIOR and pin 18 DIOW are at "L" level,
IC7506 sends REASD/WRITE to drive. (Communication is ongoing
if CS and DA
are intermittently set at LOW
.)
Are 12V and 5V applied to HDD?
Is MPEG2_PS data signal properly connected between pins of
IC7304 and IC4501?
IC7304 pin 66
→
IC4501 pin 138 OSSTD (stream data strobe)
IC7304 pins 56-59, 61, 63-65
→
IC4501 pins 3-7, 10-12
OS [7:0] (stream data)
IC7304 pin 70
←
IC4501 pin 141 OSREQ ("L" level when
IC4501 requests data transfer
.)
IC7304 pin 68
→
IC4501 pin 13 OSVLD (stream data valid)
IC7304 pin 67
→
IC4501 pin 19 OSSYNC (stream data sync)
FLOW CHART No.4
Recording is impossible (MPEG stream check)
NO
Check IC7304, IC4501 and peripheral
circuits as well as lines between pins of
IC7304 and IC4501.
YES
NO
Check IC4501, IC7506 and peripheral
circuits as well as lines between pins of
IC4501 and IC7506.
Is MPEG2_PS data signal properly connected between pins of
IC4501 and IC7506?
IC4501 pin 18
←
IC7506 pin 208 SBCLK (transfer clock 27MHz)
IC4501 pin 23
→
IC7506 pin 240 SBDA
T
(stream data)
IC4501 pin 22
→
IC7506 pin 234 SBV
ALID ("H" level when
transferred data is valid)
IC4501 pin 21
←
IC7506 pin 213 SBREQ ("H" level when
IC7506 requests data transfer)
IC4501 pin 20
→
IC7506 pin 239 SBSOS (sector head signal)
Summary of Contents for DV-HR300U
Page 25: ...25 DV HR300U M E M O ...
Page 26: ...26 27 DV HR300U DV HR300U 7 BLOCK DIAGRAMS 7 1 MAIN BLOCK DIAGRAM ...
Page 27: ...28 29 DV HR300U DV HR300U 7 2 SUB BLOCK DIAGRAM ...
Page 28: ...30 31 DV HR300U DV HR300U 7 3 POWER BLOCK DIAGRAM ...
Page 29: ...32 33 DV HR300U DV HR300U 7 4 DV BLOCK DIAGRAM ...
Page 48: ...68 DV HR300U A B C D E F G H I J 1 2 3 4 5 6 7 8 9 10 SIDE B SIDE A OPERATION R PWB ...
Page 49: ...69 DV HR300U A B C D E F G H I J 1 2 3 4 5 6 7 8 9 10 SIDE B SIDE A OPERATION L PWB ...
Page 50: ...70 DV HR300U A B C D E F G H I J 1 2 3 4 5 6 7 8 9 10 POWER PWB SIDE A ...
Page 51: ...71 DV HR300U A B C D E F G H I J 1 2 3 4 5 6 7 8 9 10 SIDE B ...
Page 52: ...72 DV HR300U A B C D E F G H I J 1 2 3 4 5 6 7 8 9 10 UV PWB SIDE A ...
Page 53: ...73 DV HR300U A B C D E F G H I J 1 2 3 4 5 6 7 8 9 10 SIDE B ...
Page 54: ...74 DV HR300U A B C D E F G H I J 1 2 3 4 5 6 7 8 9 10 LCD PWB SIDE A SIDE B ...
