Sharp 32JF-74E, Service Manual

Page: 63 / 88

63
32JF-74E
VSP9402A (IC6007)
Block Diagram
13
6
I²C
interface
(5
6
)
19
adr/tdi
s
c
l
s
da
V
DA
C
(5
4
)
U
DA
C
(5
3
)
Y
DA
C
(5
2
)
O
F
F
SET
GA
IN
76
2
79
GA
IN
O
F
F
SET
O
F
F
SET
GA
IN
AD
C1
(2
)
52
63
62
61
53 54 58 55 56 57 39 40 41 48 37 46 47
GA
IN
AD
C2
(3
)
GA
IN
S
ource
S
e
lect
(1
)
S
ource
S
e
lect
(1
6
)
38
AD
CR
(1
2
)
GA
IN
AD
CG
(1
3
)
GA
IN
AD
CB
(1
4
)
GA
IN
A
DCF
(1
5
)
GA
IN
Notch
Deskew
(4
)
Sy
n
c
(6
)
Color
Decoder
(5
)
delay
control
(P
AL
/S
E
C
AM
)
(7
)
1H delay
18
20
Ant
ial
ias,
Deskew
(1
7
)
Ant
ial
ias,
Deskew
(1
8
)
Ant
ial
ias,
Deskew
(1
9
)
Ant
ial
ias,
Deskew
(2
0
)
test-
controller
,
memo
ry
bist
(5
5
)
71
7
tc
lk
tms
69
70
xtal
o
s
cillator
(9
)
x
out
xin
divider
32 31 30 15 22 21 16 10
9
74
8
ITU
656
D
ecoder
(4
1
)
656hi
n/
cl
kf
2
0
656vin/
blank
CLK
F20
RG
B
YU
V
or
bypass
(2
5
)
τ
(2
7
)
Y
brightne
s
s
c
ontra
s
t
(2
6
)
U,
V
sat
u
rat
io
n
O
ffset,
Gain
(2
9
)
(3
0
)
soft-mix
ch
a
n
nel
mux
(3
1
)
do
w
n
sampling
2
4:4:4 4:2:2
(2
8
)
H-
pr
escaler
(3
4
)
noise
measure men
t
(3
2
)
clampin
g
cor
rection
(2
1
)
clampin
g
cor
rection
(2
2
)
clampin
g
cor
rection
(2
3
)
DC
T
I
(4
6
)
P
eaking
(4
5
)
C
o
ar
se
Delay
4:4:4
(4
9
)
ITU656
E
n
coder
(5
1
)
8
8:8:8
(5
0
)
Fin
e
de
la
y
Y noise
re
duction
(3
8
)
UV
m
oti
on
detection
(3
6
)
Y motion
detection
(3
5
)
UV
noise
re
duction
(3
7
)
eDR
AM
memory
controller
(3
9
)
14
23 17 27
Pix
elmixer
(4
4
)
H-
pos
ts
c
a
le
r
(4
2
)
Panorama
ge
ne
ra
tor
(4
3
)
V H
avout au
out
ayout
h
out
vout
cl
ko
u
t
v5
0
h50
v
cv
bs
o3
cvb
s
o
2
cvb
so
1
cv
bs
1
cv
bs
2
cv
bs
3
cv
bs
4
cv
bs
5
cv
bs
6
cv
bs
7
rin1 gi
n1
bi
n1
rin2 gi
n2
bi
n2
fbl2 fbl1
656c
lk
656i
o0
656i
o1
656i
o2
656i
o3
656i
o4
656i
o5
656i
o6
656i
o7
CLAMP CLAMP
c
lam
pi
ng
s
ig
n
a
ls
to
A
DCs
AG
C
g
ener
at
o
r
Y
d
e
la
y
(8
)
PRIMUS
(A32
)
VSP9402A VSP9432A
CLK
B3
6
Y
U,
V
C
VBS/
Y
C
YC
SEL
Y
U,
V
Y U V F
α
ma
in
in
s
e
rt
CL
KF2
P
A
D
Y
del
a
y
UV
del
a
y
UV
in
Y
in
data bu ffe r
data bu ffe r
24
res
e
t
line locked or
free-r
unnin
g
divider
line-loc
k
e
d
cl
o
c
k
s
(3
6
,
7
2
MHz)
free-running
cl
o
c
ks
(2
0.
2
5
,
40.
5
MH
z)
c
lampe
d,
f
ilt
er
d
sy
n
c
s
ig
na
l
K
c
Ky
de
t_
bl
oc
k
.v
s
d
1
/.
1
0.
20
00
D
.W
e
n
del
O
u
tput
Dat
a
Contr
o
lle
r
(5
5
)
re
a
d
con
tr
o
l
H/V-
ac
quisition
(3
3
)
In
p
u
t
Sync
Ou
tp
u
t
Sy
n
c
B
a
ck
gr
ou
nd
gen
er
a
tor
(5
7
)
O
utput
Sy
n
c
C
ont
ro
ller
(4
0
)
64
8 MH
z
DT
O
(1
0
)
LL-
P
L
L
(1
1
)
64
8
M
H
z
c
lk
2
16
M
H
z
cl
k
line
-l
o
c
ked
BL
A
N
K
BL
ANE
N
BL
ANK
FB