11 16-BiT PWM TiMeR (T16a2)
11-16
Seiko epson Corporation
S1C17153 TeChniCal Manual
(Rev. 1.0)
D0
CCaMD: T16a_CCa Register Mode Select Bit
Selects the T16A_CCA
x
register function (comparator mode or capture mode).
1 (R/W): Capture mode
0 (R/W): Comparator mode (default)
Writing 1 to CCAMD configures the T16A_CCA
x
register as the capture A register (capture mode) to
which the counter data will be loaded by the external trigger signal. When CCAMD is 0, the T16A_
CCA
x
register functions as the compare A register (comparator mode) for writing a comparison value
to generate the compare A signal.
T16a Comparator/Capture Ch.
x
a Data Register (T16a_CCa
x
)
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
T16a
Comparator/
Capture Ch.
x
a
Data Register
(T16a_CCa
x
)
0x5406
(16 bits)
D15–0
CCa[15:0]
Compare/capture A data
CCA15 = MSB
CCA0 = LSB
0x0 to 0xffff
0x0 R/W
D[15:0] CCa[15:0]: Compare/Capture a Data Bits
In comparator mode (CCAMD/ T16A_CCCTL
x
register = 0)
Sets a compare A data, which will be compared with the counter value, through this register.
When CBUFEN/T16A_CTL
x
register is set to 0, compare A data will be set to the compare A register
after a lapse of two T16A2 count clock cycles from the time when it is written to this register.
When CBUFEN is set to 1, the data written to this register is loaded to the compare A buffer. The buffer
contents are loaded into the compare A register when the compare B signal is generated.
The compare A register is always directly accessed when being read regardless of the CBUFEN setting.
The data set is compared with the counter data. When the counter reaches the comparison value set,
the compare A signal is asserted and a cause of compare A interrupt occurs. Furthermore, the TOUT
output waveform changes when TOUTAMD[1:0]/T16A_CCCTL
x
register or TOUTBMD[1:0]/T16A_
CCCTL
x
register is set to 0x2 or 0x1. These processes do not affect the counter data and the count up
operation.
In capture mode (CCAMD = 1)
When the counter value is captured at the external trigger signal (CAPA
x
) edge selected using
CAPATRG[1:0]/T16A_CCCTL
x
register, the captured value is loaded to this register. At the same time
a capture A interrupt can be generated, thus the captured counter value can be read out in the interrupt
handler.
T16a Comparator/Capture Ch.
x
B Data Register (T16a_CCB
x
)
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
T16a
Comparator/
Capture Ch.
x
B
Data Register
(T16a_CCB
x
)
0x5408
(16 bits)
D15–0
CCB[15:0]
Compare/capture B data
CCB15 = MSB
CCB0 = LSB
0x0 to 0xffff
0x0 R/W
D[15:0] CCB[15:0]: Compare/Capture B Data Bits
Sets a compare B data, which will be compared with the counter value, through this register.
When CBUFEN/T16A_CTL
x
register is set to 0, compare B data will be set to the compare B register
after a lapse of two T16A2 count clock cycles from the time when it is written to this register.
When CBUFEN is set to 1, the data written to this register is loaded to the compare B buffer. The buffer
contents are loaded into the compare B register when the compare B signal is generated.
The compare B register is always directly accessed when being read regardless of the CBUFEN setting.
The data set is compared with the counter data. When the counter reaches the comparison value set,
the compare B signal is asserted and a cause of compare B interrupt occurs. The counter is reset to 0.
Furthermore, the TOUT output waveform changes when TOUTAMD[1:0]/T16A_CCCTL
x
register or
TOUTBMD[1:0]/T16A_CCCTL
x
register is set to 0x3 or 0x1.
