11 16-BiT PWM TiMeR (T16a2)
S1C17153 TeChniCal Manual
Seiko epson Corporation
11-5
(Rev. 1.0)
4.1.2 Capture Trigger Edge Selection
Table 11.
CaPaTRG[1:0]/ CaPBTRG[1:0]
Trigger edge
0x3
Falling edge and rising edge
0x2
Falling edge
0x1
Rising edge
0x0
Not triggered
(Default: 0x0)
When a specified trigger edge is input during counting, the current counter value is loaded to the capture regis-
ter. At the same time the capture A or capture B interrupt flag is set and the interrupt signal of the timer channel
is output to the ITC if the interrupt has been enabled. This interrupt can be used to read the captured data from
the T16A_CCA
x
or T16A_CCB
x
register. For example, external event cycles and pulse widths can be measured
from the difference between two captured counter values read.
If the captured data is overwritten by the next trigger when the capture A or capture B interrupt flag has already
been set, the overwrite interrupt flag will be set. This interrupt can be used to execute an overwrite error han-
dling. To avoid occurrence of unnecessary overwrite interrupt, the capture A or capture B interrupt flag must be
reset after the captured data has been read from the T16A_CCA
x
or T16A_CCB
x
register.
notes
: • The correct captured data may not be obtained if the captured data is read at the same time
the next value is being captured. Read the capture register twice to check if the read data is
correct as necessary.
• To capture counter data properly, both the High and Low period of the CAP
x
trigger signal
must be longer than the source clock cycle time.
The setting of CAPATRG[1:0] or CAPBTRG[1:0] is ineffective in comparator mode. No counter capturing op-
eration will be performed even if a trigger edge is specified.
The capture mode cannot generate/output the TOUT signal as no compare signal is generated.
Repeat Mode and One-Shot Mode
11.4.2
T16A2 features two count modes: repeat mode and one-shot mode. The count mode is selected using TRMD /
T16A_CTL
x
register.
Repeat mode (TRMD = 0, default)
Setting TRMD to 0 sets the corresponding counter to repeat mode.
In this mode, once the count starts, the counter continues running until stopped by the application program. The
counter continues the count even if the counter returns to 0 due to a counter overflow. The counter should be set
to this mode to generate periodic interrupts at desired intervals or to generate a timer output waveform.
One-shot mode (TRMD = 1)
Setting TRMD to 1 sets the corresponding counter to one-shot mode.
In this mode, the counter stops automatically as soon as the compare B signal is generated. The counter should
be set to this mode to set a specific wait time or for pulse width measurement.
normal Clock Mode and half Clock Mode
11.4.3
T16A2 supports half clock mode to control the duty ratio of the PWM output waveform with high accuracy. In half
clock mode, T16A2 uses the dual-edge counter, which counts at the rising and falling edges of the count clock,
to compare with the compare A register. This makes it possible to control the duty ratio with double accuracy as
compared to normal clock mode.
Use HCM/T16A_CTL
x
register to select half clock mode.
normal clock mode (hCM = 0, default)
In normal clock mode, T16A2 generates a compare A signal when the T16A_TC
x
register value matches the
T16A_CCA
x
register.
