9 i/O PORTS (P)
S1C17153 TeChniCal Manual
Seiko epson Corporation
9-9
(Rev. 1.0)
• The P0 port interrupt must be disabled before setting the P0_CHAT register. Setting the
register while the interrupt is enabled may generate inadvertent P0 interrupt. Also the chat-
tering filter circuit requires a maximum of twice the check time for stabilizing the operation
status. Before enabling the interrupt, make sure that the stabilization time has elapsed.
P0 Port Key-entry Reset Configuration Register (P0_KRST)
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
P0 Port Key-
entry Reset
Configuration
Register
(P0_KRST)
0x5209
(8 bits)
D7–2
–
reserved
–
–
–
0 when being read.
D1–0
P0KRST[1:0]
P0 port key-entry reset
configuration
P0KRST[1:0]
Configuration 0x0 R/W
0x3
0x2
0x1
0x0
P0[3:0]
P0[2:0]
P0[1:0]
Disable
D[7:2]
Reserved
D[1:0]
P0KRST[1:0]: P0 Port Key-entry Reset Configuration Bits
Selects the port combination used for P0 port key-entry reset.
8.3 P0 Port Key-Entry Reset Settings
Table 9.
P0KRST[1:0]
Ports used for resetting
0x3
P00, P01, P02, P03
0x2
P00, P01, P02
0x1
P00, P01
0x0
Not used
(Default: 0x0)
The key-entry reset function performs an initial reset by inputting Low level simultaneously to the ports
selected here. For example, if P0KRST[1:0] is set to 0x3, an initial reset is performed when the four
ports P00 to P03 are simultaneously set to Low level.
Set P0KRST[1:0] to 0x0 when this reset function is not used.
notes
: • The P0 port key-entry reset function is disabled at initial reset and cannot be used for pow-
er-on reset.
• When using the P0 port key-entry reset function, make sure that the designated input ports
will not be simultaneously set to low level while the application program is running.
P
x
Port input enable Registers (P
x
_ien)
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
P
x
Port input
enable Register
(P
x
_ien)
0x520a
0x521a
(8 bits)
D7–0
P
x
ien[7:0]
P
x
[7:0] port input enable
1 Enable
0 Disable
1
(0xff)
R/W
note
: P1IEN[3:0] only are available for the P1 ports. Other bits are reserved and always read as 0.
D[7:0]
P
x
ien[7:0]: P
x
[7:0] Port input enable Bits
Enables or disables port inputs.
1 (R/W): Enable (default)
0 (R/W): disable
P
x
IEN
y
is the input enable bit that corresponds directly to the P
xy
port. Setting to 1 enables input and
the corresponding port pin input or output signal level can be read out from the P
x
_IN register. Setting
to 0 disables input.
Refer to Table 9.3.1 for more information on port input/output status, including settings other than for
the P
x
_IEN register.
