background image

Chapter 5
 
Schematics

1

1

2

2

3

3

4

4

D

D

C

C

B

B

A

A

SEG G ER

www.segger.com

J-Link

TM

Technology

Title

Size

Date:
File:

Revision

Sheet
Drawn:

A4

History / Changes

Number

J-Link-OB-STM32F103

Rev. 1.5

VK

1

1

-

/

06.11.2013
J_Link_OB_STM32F103_Rev1.5.SchDoc

TCKout

DDP

TMSout

TRSTout

TDIout

DDM

TDOin

TRESout

XIN

XOUT

GND

GND

GND

VDD, VDDA decoupling

ATTACH

LED

VCC3

(see left)

X1
8MHz

BOOT0

44

NRST

7

OSC_IN/PD0

5

OSC_OUT/PD1

6

PA0-WKUP

10

PA1

11

PA2

12

PA3

13

PA4

14

PA5

15

PA6

16

PA7

17

PA8

29

PA9

30

PA10

31

PA11

32

PA12

33

PA13/JTMS/SWDIO

34

PA14/JTCK/SWCLK

37

PA15/JTDI

38

PB0

18

PB1

19

PB2/BOOT1

20

PB3/JTDO

39

PB4/JNTRST

40

PB5

41

PB6

42

PB7

43

PB8

45

PB9

46

PB10

21

PB11

22

PB12

25

PB13

26

PB14

27

PB15

28

PC13-TAMPER-RTC

2

PC14-OSC32_IN

3

PC15-OSC32_OUT

4

VBAT

1

VDD_1

24

VDD_2

36

VDD_3

48

VDDA

9

VSS_1

23

VSS_2

35

VSS_3

47

VSSA

8

U2

STM32F103CBT6

D1

LTST-C170KGKT

J2

JTAG Disable

JTAG Selection

TRST

TDI

TMS

TCK

TDOin

GND

C2
100n

C3
100n

C4
100n

C5
100n

C1
100n

C11
100n

C7

22p*
C8

22p*

* values depend on selected crystal and layout

C6
10n

R

1

2

1

0

k

GND

R9

22R

R10

22R

R11

1k5

R8

1M*

R3

130R

R4

130R

R5

130R

R6

130R

R

1

4

7

k

R2

220R

VCC3

GND

* Note:
Pins PB8-15, PC13-15, and VBAT are not present in
VFQFPN36 package.

VCC3

*

*
*
*

*
*
*
*
*
*
*
*

RESET

GND

TCKout

DDP

TMSout

TRSTout

TDIout

DDM

TDOin

XIN

XOUT

ATTACH

LED

GND

Target MCU

USB

TRESout

TDOS

TDIS

TCKS

TMSS

RESET

VCC3

GND

V5

JTAG on board programming connector

RESET

TDIS

TDOS

1
2
3
4
5

6

7

8

9

10

T

a

g

C

o

n

n

e

c

t

J3

TC2050-IDC

TDOS

TDIS

TCKS

TMSS

TRSTS

TRSTS

Tag-Connect connector for SEGGER J-Link with
J-Link adapter from SEGGER allows supply of the
target board (V5) during programming and
debugging.

GND

Optional "JTAG Disable" jumper.
If JTAG-Disable is not needed, leave PB5 open.

TRSTS

PB5

GND

R7

130R

VCC3

J2 added, R3,R4,R5,R6,R7 changed to 130 Ohm

History / Changes

Rev. 1.0:

Rev. 1.1:

Shield1

S1

Shield2

S2

Vbus

1

D-

2

D+

3

GND

4

J1

USB_BP

VBUS

May be used to supply
5V to the board.

3.3V

VCC3

V5

Rev. 1.2:

Rev. 1.3:

Inital version

R13, R14, R15 removed

Changed MCU connections to allow use of 36 pin package
Added programming connector J3, added C11
Removed U1, C9, C10

Supply

Rev. 1.4:

Extended target signal naming for SWD, added note

(See manual for
connection of
target signals)

TDO/SWO

nRESET

TCK/SWCLK

TMS/SWDIO

TDI

nTRST

Rev. 1.5:

Moved TDOin from PA6 to PA10

J-Link-OB-STM32F103 User Guide (UM08023)

© 2004-2017 SEGGER Microcontroller GmbH

Summary of Contents for J-Link-OB-STM32F103

Page 1: ...J Link OB STM32F103 User guide of the onboard debug probe based on STM32F103 MCU Document UM08023 Revision 1 Date January 18 2018 A product of SEGGER Microcontroller GmbH www segger com...

Page 2: ...ability or fitness for a particular purpose Copyright notice You may not extract portions of this manual or modify the PDF file in any way without the prior written permission of SEGGER The software d...

Page 3: ...to us and we will try to assist you as soon as possible Contact us for further information on topics that are not yet documented Print date January 18 2018 Manual version Revision Date By Description...

Page 4: ...4 J Link OB STM32F103 User Guide UM08023 2004 2017 SEGGER Microcontroller GmbH...

Page 5: ...ns and macros that the product offers It assumes you have a working knowledge of the C language Knowledge of assembly programming is not required Typographic conventions for syntax This manual uses th...

Page 6: ...6 J Link OB STM32F103 User Guide UM08023 2004 2017 SEGGER Microcontroller GmbH...

Page 7: ...9 3 Supported target interfaces 10 3 1 Target interface pins 11 3 2 Target interface JTAG 12 3 3 Target interface SWD 13 4 Compatible MCUs as J Link OB host 14 5 Schematics 15 6 Glossary 16 J Link OB...

Page 8: ...k for eval board manufacturers J Link OB can be used with the same software package as the general J Links and can be used with the same utilities as far as the feature set of the J Link OB supports t...

Page 9: ...2 Supported target CPU cores For a list of cores supported by this J Link OB model please refer to here J Link OB Model overview J Link OB STM32F103 User Guide UM08023 2004 2017 SEGGER Microcontrolle...

Page 10: ...he following target interfaces JTAG SWD SWO It may therefore be used for ARM7 9 target CPUs or other target CPUs with JTAG connection or Cortex M targets with JTAG or Serial Wire Debug connection J Li...

Page 11: ...ET PA1 Pin 11 nTRST PA0 Pin 10 Which signals are required depends on what features shall be supported on the evaluation board If support for a specific feature or interface is not required the spare p...

Page 12: ...be connected TCK PA5 Pin 15 TMS PA7 Pin 17 TDI PA2 Pin 12 TDO PA10 Pin 31 RESET PA1 Pin 11 nTRST PA0 Pin 10 Note TCK and TMS share functionality with the SWCLK and SWDIO pins used for the SWD interfa...

Page 13: ...ed the following signals need to be connected SWCLK PA5 Pin 15 SWDIO PA7 Pin 17 SWO PA10 Pin 31 RESET PA1 Pin 11 If SWO support is not required e g when the target CPU is Cortex M0 M0 based which does...

Page 14: ...128 KB flash 20 KB RAM series MCUs The following microcontrollers are compatible to this J Link OB model STM32F103CB LQFP48 UFQPN48 VFQFPN48 STM32F103RB LQFP64 TFBGA64 STM32F103TB VFQFPN36 STM32F103V...

Page 15: ...8 1M R3 130R R4 130R R5 130R R6 130R R1 47k R2 220R VCC3 GND Note Pins PB8 15 PC13 15 and VBAT are not present in VFQFPN36 package VCC3 RESET GND TCKout DDP TMSout TRSTout TDIout DDM TDOin XIN XOUT AT...

Page 16: ...Chapter 6 Glossary This chapter describes important terms used throughout this manual J Link OB STM32F103 User Guide UM08023 2004 2017 SEGGER Microcontroller GmbH...

Page 17: ...oller in a JTAG chain TDO The electronic signal output from a TAP controller to the data sink downstream Usually the TDO signal of J Link is connected to the TDO of the last TAP controller in a JTAG c...

Page 18: ...wire debug mode J Link OB STM32F103 is able to receive the data in asynchronous mode when SWO of the target CPU is connected to the SWOin signal of J Link OB STM32F103 Normally the SWO output signal o...

Reviews: