Segger J-Link-OB-STM32F103 User Manual Download

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Chapter 3

Supported target interfaces

The J-Link-OB-STM32F103 supports the following target interfaces:
• JTAG

• SWD (+ SWO)
It may therefore be used for ARM7/9 target CPUs or other target CPUs with JTAG connection

or Cortex-M targets with JTAG or Serial Wire Debug connection.

J-Link-OB-STM32F103 User Guide (UM08023)

Summary of Contents for J-Link-OB-STM32F103

Page 1: ...J Link OB STM32F103 User guide of the onboard debug probe based on STM32F103 MCU Document UM08023 Revision 1 Date January 18 2018 A product of SEGGER Microcontroller GmbH www segger com...

Page 2: ...ability or fitness for a particular purpose Copyright notice You may not extract portions of this manual or modify the PDF file in any way without the prior written permission of SEGGER The software d...

Page 3: ...to us and we will try to assist you as soon as possible Contact us for further information on topics that are not yet documented Print date January 18 2018 Manual version Revision Date By Description...

Page 4: ...4 J Link OB STM32F103 User Guide UM08023 2004 2017 SEGGER Microcontroller GmbH...

Page 5: ...ns and macros that the product offers It assumes you have a working knowledge of the C language Knowledge of assembly programming is not required Typographic conventions for syntax This manual uses th...

Page 6: ...6 J Link OB STM32F103 User Guide UM08023 2004 2017 SEGGER Microcontroller GmbH...

Page 7: ...9 3 Supported target interfaces 10 3 1 Target interface pins 11 3 2 Target interface JTAG 12 3 3 Target interface SWD 13 4 Compatible MCUs as J Link OB host 14 5 Schematics 15 6 Glossary 16 J Link OB...

Page 8: ...k for eval board manufacturers J Link OB can be used with the same software package as the general J Links and can be used with the same utilities as far as the feature set of the J Link OB supports t...

Page 9: ...2 Supported target CPU cores For a list of cores supported by this J Link OB model please refer to here J Link OB Model overview J Link OB STM32F103 User Guide UM08023 2004 2017 SEGGER Microcontrolle...

Page 10: ...he following target interfaces JTAG SWD SWO It may therefore be used for ARM7 9 target CPUs or other target CPUs with JTAG connection or Cortex M targets with JTAG or Serial Wire Debug connection J Li...

Page 11: ...ET PA1 Pin 11 nTRST PA0 Pin 10 Which signals are required depends on what features shall be supported on the evaluation board If support for a specific feature or interface is not required the spare p...

Page 12: ...be connected TCK PA5 Pin 15 TMS PA7 Pin 17 TDI PA2 Pin 12 TDO PA10 Pin 31 RESET PA1 Pin 11 nTRST PA0 Pin 10 Note TCK and TMS share functionality with the SWCLK and SWDIO pins used for the SWD interfa...

Page 13: ...ed the following signals need to be connected SWCLK PA5 Pin 15 SWDIO PA7 Pin 17 SWO PA10 Pin 31 RESET PA1 Pin 11 If SWO support is not required e g when the target CPU is Cortex M0 M0 based which does...

Page 14: ...128 KB flash 20 KB RAM series MCUs The following microcontrollers are compatible to this J Link OB model STM32F103CB LQFP48 UFQPN48 VFQFPN48 STM32F103RB LQFP64 TFBGA64 STM32F103TB VFQFPN36 STM32F103V...

Page 15: ...8 1M R3 130R R4 130R R5 130R R6 130R R1 47k R2 220R VCC3 GND Note Pins PB8 15 PC13 15 and VBAT are not present in VFQFPN36 package VCC3 RESET GND TCKout DDP TMSout TRSTout TDIout DDM TDOin XIN XOUT AT...

Page 16: ...Chapter 6 Glossary This chapter describes important terms used throughout this manual J Link OB STM32F103 User Guide UM08023 2004 2017 SEGGER Microcontroller GmbH...

Page 17: ...oller in a JTAG chain TDO The electronic signal output from a TAP controller to the data sink downstream Usually the TDO signal of J Link is connected to the TDO of the last TAP controller in a JTAG c...

Page 18: ...wire debug mode J Link OB STM32F103 is able to receive the data in asynchronous mode when SWO of the target CPU is connected to the SWOin signal of J Link OB STM32F103 Normally the SWO output signal o...