SCS PTC-IIex, Manual

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14 Circuit Description
Chapter 14
14 Circuit Description
14.1 The Processor section
The
SCS
-PTC-IIex is designed as a 32 bit processor system, based on the
communications processor MC68360 (QUICC
7
) from Motorola. This processor contains
an expanded 32 bit core of the well known 68020 CPU, as used in many powerful
computers, together with four separate programmable serial communications ports, the
so-called SCC's. One of these SCC's serve as the interfaces to the DSP for Packet-Radio
operation and is able to do the HDLC protocol inclusive CRC calculation independently
from others.
One SCC is used as an RS232 interface to the terminal. A buffer chip MAX207A is
superposed, which provides the correct RS232 voltage levels and is used as a buffer. The
serial interface is totally implemented and has all handshake wires. The baud rate to the
terminal (max. 115 kBaud) is detected automatically and needs not be set.
Four RAM chips with eight bits each are required to cover the 32 bit wide data bus. The
PTC-IIex has of 2 MByte of static RAM, which plays a large part in running the mailbox
and internal administration.
A flash memory with 256 kByte contains the software of the PTC-IIex as a compressed
file. The firmware can easily be updated using the serial RS232 link to the computer. No
chips need to be changed.
After switching on the PTC-IIex the operation software is expanded from the 8-bit flash,
loaded in the 32 bit static RAM (boot) and started. The operation software uses the 32 bit
data bus and runs with the maximum possible CPU speed.
Operating parameters for the PTC-IIex, that should be resistant even to a deep reset, are
also stored in the flash memory. Data in this kind of memory remains stored, even when
no voltage is applied, but contrary to an EPROM, may be electrically erased and re-
written whilst in circuit. A battery backed up real time clock and other features of the
previous PTC are, of course, still included.
14.2 The shortwave modem with signal processor
The DSP5303 DSP from Motorola forms the interface to the shortwave transceiver. It
runs with a clock frequency of 100 MHz and performs 100 MIPS. As the clock frequency
is programmable, it is automatically adjusted to suit the work of the moment. For easy
tasks, such as FSK, the processing speed can be reduced, yielding a corresponding saving
in energy. The DSP contains a built-in 16 bit digital to analog converter, with the help of
which the audio output signal to the transceiver is generated, be it simple (A)FSK, or the
complex phase modulation of PACTOR-II and PACTOR-III. The output amplitude is
also programmable and may be set in the range between 30 mV and 3 Vpp in 1 mV steps
by software command. The normally required MIC Gain potentiometer is thus missing.
7
Quad Integrated Communication Controller
166