Schweitzer Engineering Laboratories SEL-700G Series, Instruction Manual

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H.5
Date Code 20170814 Instruction Manual SEL-700G Relay
Synchrophasors
Settings for Synchrophasors
Certain settings in Table H.1 are hidden, depending on the status of other
settings. For example, if PHDATAI := NA, the IXCOMP and IYCOMP
settings are hidden to limit the number of settings for your synchrophasor
application.
Definitions for the settings in Table H.1 are as follows:
MRATE
Selects the message rate in messages per second for synchrophasor data
streaming on serial ports.
Choose the MRATE setting that suits the needs of your PMU application. This
setting is one of seven settings that determine the minimum port SPEED
necessary to support the synchrophasor data packet rate and size. See
Communications Bandwidth on page H.16 for detailed information.
PMAPP
Selects the type of digital filters used in the synchrophasor algorithm:
➤
The Narrow Bandwidth setting (N) represents filters with a
cutoff frequency approximately ¼ of MRATE. The response in
the frequency domain is narrower, and response in the time
domain is slower. This method results in synchrophasor data that
are free of aliasing signals and well suited for post disturbance
analysis.
➤
The Fast Response setting (F) represents filters with a higher
cutoff frequency. The response in frequency domain is wider and
the response in the time domain is faster. This method results in
synchrophasor data that you can use in synchrophasor
applications requiring more speed in tracking system
parameters.
PHCOMP
Enables or disables frequency-based compensation for synchrophasors. For
most applications, set PHCOMP := Y to activate the algorithm that
compensates for the magnitude and angle errors of synchrophasors for
frequencies that are off nominal. Use PHCOMP := N if you are concentrating
the SEL-700G synchrophasor data with other PMU data that do not employ
frequency compensation.
NUMDSW Number of 16-bit Digital Status
Words (0, 1) 0
TREA1 Trigger Reason Bit 1 (SEL
OGIC
) TRIP OR ER
TREA2 Trigger Reason Bit 2 (SEL
OGIC
) 81T OR 81RT OR BNDT
TREA3 Trigger Reason Bit 3 (SEL
OGIC
) 59PX1T OR 59PX2T OR
59PY1T OR 59PY2T
TREA4 Trigger Reason Bit 4 (SEL
OGIC
) 27PX1T OR 27PX2T OR
27PY1T OR 27PY2T
PMTRIG Trigger (SEL
OGIC
) TREA1 OR TREA2 OR
TREA3 OR TREA4
IRIGC IRIG-B Control Bits Definition
(NONE, C37.118) NONE
a
Set EPMU := Y to access the remaining settings.
Table H.1 PMU Settings in the SEL-700G for C37.118 Protocol in Global
Settings (Sheet 2 of 2)
Setting Description Default