9-16
Event Reports and Sequential Events Reporting
Date Code 20010521
SEL-387E Instruction Manual
Column Symbol
Definition
TH5 p
T
TH5 asserted
TH5 asserted longer than TH5D
REF P
T
1
.
32IF*50G4*!REFP asserted (timing to trip)
32IF*50G4*REFP asserted (timed out)
Timing 1 cycle to reset after REFP assertion
Reset
TRP 12
1
2
b
TRIP1 asserted
TRIP2 asserted
TRIP1 and TRIP2 asserted
TRP 34
3
4
b
TRIP3 asserted
TRIP4 asserted
TRIP3 and TRIP4 asserted
Set 1
V1
V2
V3
V4
p
T
d
S1Vn asserted (timing to output)
S1VnT asserted (timed out); S1Vn asserted
S1VnT asserted, S1Vn deasserted (timing to reset)
Set 1
LT 12
1
2
b
Latch Bit 1 Latched
Latch Bit 2 Latched
Latch Bit 1 and Latch Bit 2 Latched
Set 1
LT 34
3
4
b
Latch Bit 3 Latched
Latch Bit 4 Latched
Latch Bit 3 and Latch Bit 4 Latched
Set 2
V1
V2
V3
V4
p
T
d
S2Vn asserted (timing to output)
S2VnT asserted (timed out); S2Vn asserted
S2VnT asserted, S2Vn deasserted (timing to reset)
Set 2
LT 12
1
2
b
Latch Bit 1 Latched
Latch Bit 2 Latched
Latch Bit 1 and Latch Bit 2 Latched
Set 2
LT 34
3
4
b
Latch Bit 3 Latched
Latch Bit 4 Latched
Latch Bit 3 and Latch Bit 4 Latched
