
6-24
Close and Reclose Logic
Date Code 20020215
SEL-351R Instruction Manual
If the line is energized, channel VS overvoltage element 59S1 can be set to assert. Make the
following setting:
79STL
= 59S1 + ...
If line voltage is present, Relay Word bit 59S1 asserts, stalling open interval timing (reclose
block). If line voltage is not present, Relay Word bit 59S1 deasserts, allowing open interval
timing to proceed (unless some other set condition stalls open interval timing).
Additional Settings Example 3
Refer to Figure 6.4 and accompanying setting example, showing an application for setting
79STL.
Other Settings Considerations
If no special skip shot or stall open interval timing conditions are desired, make the following
settings:
79SKP =
0
(numeral
0)
79STL =
0
(numeral
0)
Block Reset Timing Setting (79BRS)
The block reset timing setting 79BRS keeps the reset timer from timing. Depending on the
reclosing relay state, the reset timer can be loaded with either reset time:
79RSD (Reset Time from Reclose Cycle)
or
79RSLD (Reset Time from Lockout)
Depending on how setting 79BRS is set, none, one, or both of these reset times can be
controlled. If the reset timer is timing and then 79BRS asserts to:
79BRS =
logical
1
reset timing is stopped and does not begin timing again until 79BRS deasserts to:
79BRS =
logical
0
When reset timing starts again, the reset timer is fully loaded. Thus, successful reset timing has
to be continuous. Use the RSTMN Relay Word bit to monitor reset timing (see
Open Interval and Reset Timing
Example 1
The block reset timing setting is:
79BRS
= (51P + 51G) * 79CY
Relay Word bit 79CY corresponds to the Reclose Cycle State. The reclosing relay is in one of
the three reclosing relay states at any one time (see Figure 6.5 and Table 6.1).
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