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COMe-bTL6 - User Guide. Rev. 1.5
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6.4.3.2.
Chipset PCH-IO Configuration Setup Menu
Figure 17: Chipset PCH-IO Configuration Setup menu Initial Screen
The following table shows the Chipset PCH-IO Configuration sub-screens and describes the functions. Default
settings are in bold.
Table 46: Chipset> PCH-IO Configuration> Menu Sub-screens and Functions
Function
Second level Sub-Screen/Description
PCI Express
Configuration>
COMe PCIe mapping scheme
8x1 (standard)
Port8xh Decode
[Enabled, Disabled]
PCIe Root Port> 1,2,3,4,10,11, 21, 22, 23, 24>
(Not mapped to COMe line)
PCI Root Port 5 (COM Lane 0)>
PCI Root Port 6 (COM Lane 1)>
PCI Root Port 7 (COM Lane 2)>
PCI Root Port 8 (COM Lane 3)>
PCI Root Port 17 (COM Lane 4)>
PCI Root Port 18 (COM Lane 5)>
PCI Root Port 19 (COM Lane 6)>
PCI Root Port 20 (COM Lane 7)>
PCI Root Port 9 (opt. device)>
PCI Root Port 12 (on-module Ethernet)>
PCIe Root Port 13, 14, 15, 16>
(Configured as USB/SATA)
PCI Express.
Root Port #
Control the PCIe 4.0 Root port.
[Enabled, Disabled]
Connection Type Selects the connection type to
root port.
[Built-in, Slot]
ASPM
Set ASPM level
[Disabled, L0s, L1, L0sL1, Auto]
PME SCI
[Enabled, Disabled]
Hotplug
[Enabled, Disabled]
PCIe Speed
Configure PCIe Speed
[Auto, Gen 1, Gen 2, Gen 3]
Detect Timeout
Value in msec the reference
code waits for link to exit
Detect State for enabled port
before assuming there is no