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2. SGH-N620E Circuit Description
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2-1
1. SGH-
N620E
RF Circuit Description
1) RX PART
1. ASM(U301)
→
Switching Tx, Rx path for GSM900, DCS1800 by logic controlling.
2. ASM Control Logic (Q301,Q302,Q303)
→
Truth Table
VC1
VC2
GSM Tx Mode
L
H
DCS Tx Mode
H
L
GSM Rx Mode
L
L
DCS Rx Mode
L
L
3. FILTER
To convert Electromagnetic Field Wave to Acoustic Wave and then pass the specific frequency band.
- DCS FILTER (F301,C305,C307,L303)
→
For filtering the frequency band between 1805 ~ 1880 MHz
- GSM FILTER (F302,C210,C312,L306)
→
For filtering the frequency band between 925 ~ 960MHz
4. VC-TCXO (OSC301)
To generate the 13MHz reference clock to drive the logic and RF. After additional process, the reference clock applies to
the U304 Rx IQ demodulator and U302 Tx IQ modulator. The oscillator for RX IQ demodulator and Tx modulator are
controlled by serial data to select channel and use fast lock mode for GPRS high class operation.
5. Si 4200F (U302)
This chip integrates two differential-input LNAs.
The GSM input supports the E-GSM, DCS input supports the DCS1800. The LNA inputs are matched to the 200 ohm
differential output SAW filters through external LC matching network.
Image-reject mixer downconverts the RF signal to a 100 KHz intermediate frequency(IF) with the RFLO from SI4133T
frequency synthesizer. The RFLO frequency is between 1737.8 ~ 1989.9 MHz.
The Mixer output is amplified with an analog programmable gain amplifier(PGA), which is controlled by AGAIN.
The quadrature IF signal is digitized with high resolution A/D converts (ADC).
6. Si 4201BM (U304)
The SI4201BM down-converts the ADC output to baseband with a digital 100 KHz quadrature LO signal. Digital
decimation and IIR filters perform channel selection to remove blocking and reference interface signals.
After channel selection, the digital output is scaled with a digital PGA, which is controlled with the DGAIN. DACs drive
a differential analog signal onto the RXIP, RXIN, RXQP, RXQN pins to interface to standard analog-input baseband IC.
2) TX PART
Baseband IQ signal fed into offset PLL, this function is included inside of U305 chip. SI4200F chip generates modulator
signal which power level is about 6.5dBm and fed into Power Amplifier(U303). The PA output power and power ramping
are well controlled by Auto Power Control circuit. We use offset PLL below