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SGH-D800 Flow Chart of Troubleshooting
2-
7
This Document can not be used without Samsung's authorization
C217
V
S
S
6
V
S
S
7
H
10
H
11
V
S
S
8
V
S
S
9
H
12
V
S
S
A
_D
R
1
1
V
S
S
A
_U
F
18
X
1
R
T
C
H
19
F
1
9
X
2
R
T
C
V
S
S
1
2
V
S
S
1
3
L
8
M
8
V
S
S
1
4
V
S
S
1
5
M
9
M
1
0
V
S
S
1
6
V
S
S
1
7
M
1
1
M
1
2
V
S
S
1
8
A
18
V
S
S
2
V
S
S
3
G
8
G
9
V
S
S
4
V
S
S
5
H
8
H
9
B
16
V
D
D
_
IO
_
1
P
8
_
4
V
D
D
_
IO
_
1
P
8
_
5
C
1
C
14
V
D
D
_
IO
_
1
P
8
_
6
V
D
D
_
IO
_
1
P
8
_
7
D
9
D
18
V
D
D
_
IO
_
1
P
8
_
8
V
D
D
_
IO
_
1
P
8
_
9
F
1
G
18
V
R
T
C
V
S
S
1
A
2
J
1
2
V
S
S
1
0
V
S
S
1
1
K
8
L
7
V
D
D
_
IO
_
1
P
8
_
1
0
V
D
D
_
IO
_
1
P
8
_
1
1
L
16
P
1
V
D
D
_
IO
_
1
P
8
_
1
2
V
D
D
_
IO
_
1
P
8
_
1
3
T
18
U
1
V
D
D
_
IO
_
1
P
8
_
1
4
V
D
D
_
IO
_
1
P
8
_
1
5
U
5
U
12
V
D
D
_
IO
_
1
P
8
_
1
6
V
D
D
_
IO
_
1
P
8
_
1
7
W
8
W
18
V
D
D
_
IO
_
1
P
8
_
1
8
B
6
V
D
D
_
IO
_
1
P
8
_
2
V
D
D
_
IO
_
1
P
8
_
3
B
12
V
D
D
A
_D
F
17
V
D
D
A
_U
V
D
D
_
C
O
R
E
1
B
8
B
13
V
D
D
_
C
O
R
E
2
V
D
D
_
C
O
R
E
3
G
2
H
18
V
D
D
_
C
O
R
E
4
V
D
D
_
C
O
R
E
5
M
2
N
18
V
D
D
_
C
O
R
E
6
V
D
D
_
C
O
R
E
7
V
7
V
1
3
V
D
D
_
C
O
R
E
8
V
D
D
_
IO
_
1
P
8
_
1
B
4
L
4
TCK
U14
V14
TDI
TDO
T12
TEST1 U15
T14
TEST2
TEST3 V16
T
M
S
W
14
R
1
2
T
R
S
T
N
T
X
0
M
3
T
X
1
K
7
T
11
R
X
1
_
IR
Q
28
S
IM
C
LK
P
4
T
2
S
IM
IO
R
3
S
P
C
L
K
0
M18
SPCLK1_PIO18
T
3
S
P
F
S
0
SPFS1_PIO15
N15
S
P
R
X
D
0
R
4
SPRXD1_PIO17
M17
S
P
T
X
D
0
_
I2
SD
U
2
N16
SPTXD1_I2SD_PIO16
P
IO
4
1
_
IR
D
A
TX
P
IO
4
2
_
IR
D
A
RX
R
1
7
N
14
P
IO
4
3
_
M
C
I_
D
A
T
0
_
EN
J16
PIO47
G
5
P
W
M
1
_
P
IO
46
R
E
S
T
N
G
15
R
IO
_
P
IO
0
1
P
3
R
T
C
A
L
A
R
M
N
H
17
N
2
R
T
S
0
_
P
IO
0
4
V6
RWN
M
1
R
X
0
_
IR
Q
28
L
6
P12
PIO31_IRQ6
P
IO
32
R
1
3
U18
PIO33
PIO34
R14
PIO35_A_A25_BOOTSE L
F2
F
1
6
P
IO
3
6
_
U
S
B
_
O
E
N
P
IO
3
7
_
U
S
B
_
D
A
T
A
E
17
J
1
5
P
IO
3
8
_
M
C
I_
C
L
K
L
1
4
P
IO
3
9
_
M
C
I_
C
M
D
_
E
N
P
IO
4
0
_
M
C
I_
D
A
T
_
E
N
M
14
R
1
6
P
IO
1
9
_
P
W
R
K
E
E
P
P
IO
2
0
_
S
Y
S
C
L
K
R
E
Q
P
19
K
13
P
IO
2
1
_
M
C
I_
D
A
T
0
P
IO
2
2
_
M
C
I_
D
A
T
1
L
1
2
L
1
3
P
IO
2
3
_
M
C
I_
D
A
T
2
P
IO
2
4
_
M
C
I_
D
A
T
3
L
1
5
V
19
P
IO
25
P
IO
26
U
16
P
IO
27
U
19
W
17
P
IO
28
E14
PIO30_WAITN
2
G
16
O
S
C
3
2
O
U
T
PIO00_IRQ5 P16
P
IO
0
7
_
U
S
B
_
S
U
S
P
B
19
P
IO
0
8
_
M
C
I_
C
M
D
J
1
3
C
19
P
IO
0
9
_
U
S
B
_
V
P
I
P
IO
10
V
17
P
IO
1
1
_
U
S
B
_
V
M
I
C
18
D
17
P
IO
1
2
_
U
S
B
_
V
P
O
P
IO
1
3
_
U
S
B
_
V
M
O
E
16
P
5
P
IO
1
4
_
S
IM
R
S
T
P
15
K
E
Y
B
R
D
11
H
2
J
5
K
E
Y
B
R
D
2
K
E
Y
B
R
D
3
J
4
J
8
K
E
Y
B
R
D
4
K
E
Y
B
R
D
5
_
P
S
W
1
_
B
U
F
H
6
H
4
K
E
Y
B
R
D
6
K
E
Y
B
R
D
7
H
1
H
3
K
E
Y
B
R
D
8
K
E
Y
B
R
D
9
G
6
1
N
C
1
N
C
2
INT0
IO
W6
V12
IOBIT0_PIO05
IOBIT1_PIO06
N11
IRQ1
M16
M19
IRQ2
IRQ3
P17
P18
IRQ4
J
7
K
E
Y
B
R
D
0
K
E
Y
B
R
D
1
J
6
G
4
K
E
Y
B
R
D
10
D_D14
D_D15
P11
R7
D_D2
D_D3
T7
R8
D_D4
D_D5
V8
U8
D_D6
D_D7
T8
T9
D_D8
D_D9
R9
FLASHRSTN
H14
T15
D_A5
T5
V4
D_A6
D_A7
N6
R6
D_A8
U6
D_D0
D_D1
T6
P8
D_D10
D_D11
P9
N8
D_D12
D_D13
N9
N10
CKO_IACK
T17
CPTSTSTOP_CK O
C
T
S
0
_
P
IO
2
9
M
6
N
5
D
C
D
0
_
P
IO
4
4
P
2
D
S
R
0
_
P
IO
0
2
D
T
R
0
_
P
IO
0
3
N
4
V1
D_A0
D_A1
W2
W3
D_A2
D_A3
V3
U4
D_A4
A_D2
A_D3
G10
G11
A_D4
A_D5
F11
E11
A_D6
A_D7
G12
D11
A_D8
A_D9
E12
A_OEN
B14
D14
A_WEN
W
12
C
K
I
N12
F15
A_CS6N
A_CS7N
B17
A8
A_D0
A_D1
E9
C12
A_D10
A_D11
A12
F12
A_D12
A_D13
D12
E13
A_D14
A_D15
D13
F9
E7
C4
A_A8
A_A9
C2
H16
A_BE0N
A_BE1N
A17
A14
A_CS0N
A_CS1N
C15
G14
A_CS2N
A_CS3N
J14
D15
A_CS4N
A_CS5N
C16
D2
A_A2
D8
E4
A_A20
A_A21
E3
F5
A_A22
A_A23
F4
F3
A_A24
A_A3
A6
C6
A_A4
A_A5
C5
D7
A_A6
A_A7
A_A1
C8
A3
A_A10
A_A11
B3
B1
A_A12
A_A13
D6
D5
A_A14
A_A15
D3
E8
A_A16
A_A17
F8
A_A18
E6
A_A19
U201
M4
ATCK_CTS1
ATDI_RTS1 L5
T13
ATDO_PWM2
ATMS_PIO45 K12
B7
A_A0
VCCD_1_5
C204
1
OSC20
0
2
VCCD_1_8
C216
VRTC
DSP_TMS
TR_RST
DEBUG_TXD
SDS_TXD
DSP_RWN
DEBUG_RXD
SDS_RXD
SIMCLK
SIMDATA
UP_SCLK
PCM_CLK
UP_CS
PCM_SYNC
UP_SDO
PCM_RXD
UP_SDI
PCM_TXD
DSP_TCK
DSP_TDI
DSP_TDO
USB_VPO
USB_VMO
SIMRST
PWR_KEEP
XOENAQ
CODEC_PDN
AS2
EAR_SWITCH
NAND_INT
AS4
CF
USB_CON
USB_OEN
USB_DATA
AS3
UPPER_EL_EN
BL_CONT
CHG_EN
RTCALARM
DEBUG_RTS
KEY_COL(0)
KEY_COL(1)
KEY_ROW(4)
KEY_ROW(5)
KEY_COL(2)
KEY_COL(3)
KEY_COL(4)
PSW1_BUF
KEY_ROW(0)
KEY_ROW(1)
KEY_ROW(2)
KEY_ROW(3)
CLK32K
FLIP_SNS
USB_SUSP
USB_DET
AMP_EN
DSP_DB(2)
DSP_DB(3)
DSP_DB(4)
DSP_DB(5)
DSP_DB(6)
DSP_DB(7)
DSP_DB(8)
DSP_DB(9)
DSP_INT
DSP_IO
USB_CHG_EN
CHG_COMPLETE
INTRQ
JACK_INT
YMU_IRQ
HERA_INT
DSP_AB(1)
DSP_AB(2)
DSP_AB(3)
DSP_AB(4)
DSP_AB(5)
DSP_AB(6)
DSP_AB(7)
DSP_AB(8)
DSP_DB(0)
DSP_DB(1)
DSP_DB(10)
DSP_DB(11)
DSP_DB(12)
DSP_DB(13)
DSP_DB(14)
DSP_DB(15)
A(18)
A(17)
A(16)
A(15)
A(14)
A(13)
A(12)
A(11)
A(10)
A(1)
A(0)
CP_TCK
CP_TDI
CP_TDO
CP_TMS
CLK13M_TR
DEBUG_CTS
MAIN_EL_EN
BT_EN
M_HOLD
DSP_AB(0)
D(2)
D(15)
D(14)
D(13)
D(12)
D(11)
D(10)
D(1)
D(0)
YMU_CS
HERA_CS
RAM1_CS
ONENAND_CS
ROM1_CS
UPPER_BYTE
LOWER_BYTE
A(9)
A(8)
A(7)
A(6)
A(5)
A(4)
A(3)
A(24)
A(23)
A(22)
A(21)
A(20)
A(2)
A(19)
CHG_DET
FLASH_RESET
CP_WEN
CP_OEN
D(9)
D(8)
D(7)
D(6)
D(5)
D(4)
D(3)
A(0:24)
D(0:15)
DSP_DB(0:15)
DSP_AB(0:8)
KEY_COL(0:4)
KEY_ROW(0:5)
Summary of Contents for SGH-D800
Page 48: ...6 1 6 SGH D800 Block Diagrams ...
Page 49: ...SGH D800 Block Diagrams 6 2 ...