S5PC110_UM
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
1-6
Table 1-1 Interrupts in Connection with FIFO
Type
FIFO Mode
Non-FIFO Mode
Rx interrupt
Generated if Rx FIFO count is greater than or equal
to the trigger level of received FIFO.
Generated if the number of data in FIFO does not
reaches Rx FIFO trigger Level and does not
receive any data during 3-word time (receive time
out). This interval follows the setting of Word
Length bit.
Generated by receive holding register
whenever receive buffer becomes full.
Tx interrupt
Generated if Tx FIFO count is less than or equal to
the trigger level of transmit FIFO (Tx FIFO trigger
Level).
Generated by transmit holding register
whenever transmit buffer becomes
empty.
Error
interrupt
Generated if frame error, parity error, or break
signal are detected.
Generated if UART receives new data when Rx
FIFO is full (overrun error).
Generated by all errors. However if
another error occurs at the same time,
only one interrupt is generated.
1.3.8 UART ERROR STATUS FIFO
UART contains the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data,
among FIFO registers is received with an error. An error interrupt is issued only if the data containing an error, is
ready to read out. To clear the error status FIFO, URXHn with an error and UERSTATn must be read out.
For example, it is assumed that the UART Rx FIFO receives A, B, C, D, and E characters sequentially and the
frame error occurs while receiving 'B' and the parity error occurs while receiving 'D'.
The actual UART receive error does not generate any error interrupt, since the character, which was received with
an error was not read. The error interrupt occurs if the character is read out.
Time
Sequence Flow
Error Interrupt
Note
#0
If no character is read out
-
#1
A, B, C, D, and E is received
-
#2
After A is read out
Frame error (in B) interrupt occurs.
The 'B' has to be read out.
#3
After B is read out
-
#4
After C is read out
Parity error (in D) interrupt occurs.
The 'D' has to be read out.
#5
After D is read out
-
#6
After E is read out
-
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...