S5PC110_UM
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
1-3
1.3 UART DESCRIPTION
The following sections describe UART operations, such as data transmission, data reception, interrupt generation,
baud-rate generation, loop-back mode, infrared modes, and auto flow control.
1.3.1 DATA TRANSMISSION
The data frame for transmission is programmable. It consists of a start bit, five to eight data bits, an optional parity
bit, and one to two stop bits, specified by the line control register (ULCONn). The transmitter can also produce a
break condition that forces the serial output to logic 0 state for one frame transmission time. This block transmits
the break signals after the present transmission word is transmitted completely. After the break signal
transmission, the transmitter continuously transmits data to Tx FIFO (Tx holding register, in case of Non-FIFO
mode).
1.3.2 DATA RECEPTION
Similar to data transmission, the data frame for reception is also programmable. It consists of a start bit, five to
eight data bits, an optional parity bit, and one to two stop bits in the line control register (ULCONn). The receiver
detects overrun error, parity error, frame error and break condition, each of which sets an error flag.
•
Overrun error indicates that new data has overwritten the old data before the old data was read.
•
Parity error indicates that the receiver has detected an unexpected parity condition.
•
Frame error indicates that the received data does not have a valid stop bit.
•
Break condition indicates that the RxDn input is held in the logic 0 state for more than one frame transmission
time.
Receive time-out condition occurs if no data is received during the 3-word time (this interval follows the setting of
Word Length bit) and the Rx FIFO is not empty in the FIFO mode.
1.3.3 AUTO FLOW CONTROL (AFC)
The UART0 and UART1 in S5PC110 support auto flow control (AFC) using nRTS and nCTS signals. UART2
supports auto flow control if TxD3 and RxD3 are set as nRTS2 and nCTS2 by GPA1CON(GPIO SFR). In this
case, it can be connected to external UARTs. To connect UART to a Modem, disable the AFC bit in UMCONn
register and control the signal of nRTS using software.
In AFC, the nRTS signal depends on the condition of the receiver, whereas the nCTS signals control the operation
of transmitter. The UART's transmitter transfers the data to FIFO if nCTS signals are activated (in AFC, nCTS
signals means that other UART's FIFO is ready to receive data). Before UART receives data, the nRTS signals
must be activated if its receive FIFO has more than 2-byte as spare. The nRTS signals must be inactivated if its
receive FIFO has less than 1-byte as spare (in AFC, the nRTS signals means that its own receive FIFO is ready to
receive data).
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...