Samsung S5PC110, Manual

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S5PC110_UM 6 EXTERNAL BUS INTERFACE
6-1
6
EXTERNAL BUS INTERFACE
6.1 OVERVIEW OF EXTERNAL BUS INTERFACE
The External Bus Interface (EBI) is used as a peripheral in S5PC110. It relies on memory controller to release
external requests for external bus when the memory controller is idle, since it has no knowledge of when memory
access will begin or complete. It enables one SROM controller, one OneNAND controller, and one NAND Flash
controller, to share an external memory bus, Memory Port 0.
6.2 KEY FEATURES OF S5PC110 EBI
The key features of S5PC110 EBI include:
Memory Port 0 is shared using EBI.
* Reference: ARM PrimeCell External Bus Interface (PL220) and ARM DDI 0249B.
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Three memory controllers (SROMC, OneNANDC, and NFCON) share the pad interface.
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Priority determines the pad interface ownership (can be changed).
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The handshaking between EBI and memory controller consists of a three-wire interface: EBIREQ, EBIGNT,
and EBIBACKOFF (all Active High).
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The memory controllers assert EBIREQ signals when they require external bus access.
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The arbitrated EBIGNT is issued to the memory controller with highest priority.
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The memory controller must complete the current transfer and release the bus. To signal these actions,
EBIBACKOFF is made the output of EBI.
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The EBI arbitration scheme tracks the memory controller that is currently granted and waits for the transaction
from the memory controller to finish (EBIREQ is set to Low by the memory controller) before it grants the next
memory controller. If a higher priority memory controller requests the bus, then EBIBACKOFF signal informs
the currently granted memory controller to terminate the current transfer as soon as possible.
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The System Controller provides booting method and CS selection information to Memory Subsystem.
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nCS0 and nCS1 in memory port 0 are only reserved for SROMC.
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If NAND Flash or OneNAND is selected for boot device, nCS2 is used to access the boot media.
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EBIGNT is required to be deasserted one cycle after EBIREQ is deasserted in sync. mode.
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EBIBACKOFF is required to be deasserted one cycle after EBIREQ is deasserted in sync. mode.
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In case EBIREQ is deasserted because of higher priority EBIBACKOFF, EBIREQ signal must be set to low for
at least one clock cycle in sync. mode.
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EBI_REQ duration is not required for at least 4 cycles from CSYSREQ to CACTIVE