S5PC110_UM
4 NAND FLASH CONTROLLER
4-13
4.3.12 LOCK SCHEME FOR DATA PROTECTION
NFCON provides a lock scheme to protect data stored in external NAND Flash memories from malicious program.
For this scheme, the NFSBLK and NFEBLK registers are used to provide access control methods; only the
memory area between NFSBLK and NFEBLK is erasable and programmable, but the read access is available to
whole memory area.
This lock scheme is only available when you enable LockTight(NFCONT[17]) and LOCK(NFCONT[16]).
1. Unlock
mode
In unlock mode, user can access whole NAND memory; there are no constraints to access memory.
2. Soft lock mode
In soft lock mode, you can access NAND block area between NFSBLK and NFEBLK.
When you try to program or erase the locked area, an illegal access error will occur (NFSTAT [5] bit will be
set).
3. Lock-tight
mode
In lock-tight mode, you can access NAND block area between NFSBLK and NFEBLK as soft lock mode. The
differences is that you cannot change NFSBLK and NFEBLK registers, and also LOCK(NFCONT[16]) and
LockTight(NFCONT[17]) bits.
When you try to program or erase the locked area, an illegal access error will occur (NFSTAT[5] bit will be set).
The LockTight(NFCONT[17]) bit is only cleared when reset or wake up from sleep mode (It is impossible to clear it
by software).
The accessibility of NAND area is illustrated in the figure below.
when Lock-tight =1
or SoftLock=1
NAND flash memory
Locked area
(Read only)
Prorammable/
Readable
Area
Locked area
(Read only)
Address
High
Low
1
NFEBLK
NFSBLK
NFEBLK
Locked Area
(Read only)
When NFSBLK=NFEBLK
NFSBLK
NFSBLK - 1
NOTE:
If the address of NFSBLK and NFEBLK are same, then the erase and program to all NAND memory are not allowed.
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...