S5PC110_UM
4 NAND FLASH CONTROLLER
4-9
4.3.8 4-BIT ECC PROGRAMMING GUIDE (DECODING)
1. To use 4-bit ECC in software mode, set the MsgLength to 0 (512-byte message length) and the ECCType to
“10” (enable 4-bit ECC). ECC module generates ECC parity code for 512-byte read data. Therefore, to reset
ECC value write the InitMECC (NFCONT[5]) bit as ‘1’ and clear the MainECCLock (NFCONT[7]) bit to
‘0’(Unlock) before reading data.
MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not.
2. Whenever data is read, the 4-bit ECC module generates ECC parity code internally.
3. After you complete reading 512-byte (not including spare area data), you must read parity codes. MLC ECC
module needs parity codes to detect whether error bits have occurred or not. Therefore, you must read ECC
parity code immediately after reading 512-byte. After ECC parity code is read, 4-bit ECC engine starts
searching for error internally. 4-bit ECC error searching engine needs minimum of 155 cycles to find any error.
During this time, you can continue reading main data from external NAND Flash memory. Use
ECCDecDone(NFSTAT[6]) to check whether ECC decoding is completed or not.
4. When ECCDecDone (NFSTAT[6]) is set (‘1’), NFECCERR0 indicates whether error bit exists or not. If any
error exists, refer NFECCERR0/1 and NFMLCBITPT registers to fix.
5. If you have more main data to read, go back to step 1.
6. To check meta data error, set the MsgLength to 1 (24-byte message length) and the ECCType to ‘1’ (enable
4-bit ECC). ECC module generates ECC parity code for 512-byte read data. Therefore, you must reset ECC
value by writing the InitMECC (NFCONT[5]) bit as ‘1’ and clear the MainECCLock (NFCONT[7]) bit to
‘0’(Unlock) before reading data.
MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not.
7. Whenever data is read, the 4-bit ECC module generates ECC parity code internally.
8. After you complete reading 512-byte (not include spare area data), you must read parity codes. 4-bit ECC
module needs parity codes to detect whether error bits have occurred or not. Therefore, ensure to read ECC
parity codes immediately after reading 512-byte. After ECC parity code is read, 4-bit ECC engine starts
searching for error internally. 4-bit ECC error searching engine needs minimum of 155 cycles to find any error.
During this time, you can continue reading main data from external NAND Flash memory. Use
ECCDecDone(NFSTAT[6]) to check whether ECC decoding is completed or not.
9. When ECCDecDone (NFSTAT[6]) is set (‘1’), NFECCERR0 indicates whether error bit exists or not. If any
error exists, you can fix it by referring to NFECCERR0/1 and NFMLCBITPT registers.
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...