Samsung S5PC110, Manual

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S5PC110_UM 3 ONENAND CONTROLLER
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3.8.4 INTERRUPT CONTROLLER REGISTERS
Interrupt controller registers can be classified into following four register types: 1) interrupt pending registers, 2)
interrupt status registers, 3) interrupt mask registers, and 4) interrupt clear registers.
Each interrupt pending register represents the raw status of the interrupt sources such as DMA transfer done,
DMA transfer error, and OneNAND INT pin done. Interrupt pending register is the exact copy of the peripheral
device status registers (ONENAND_IF_STATUS, DMA_TRANS_STATUS, and SQC_STATUS). Therefore, if the
raw status bit of the peripheral device status register is cleared by writing a clear command to the peripheral
device command register (ONENAND_IF_CMD, DMA_TRANS_CMD, and SQC_CMD), the corresponding bit of
the interrupt pending register is also cleared automatically.
For example, let us consider a DMA operation scenario, in which the DMA engine generates an interrupt and this
interrupt is cleared.
After DMA transfer is successfully completed, the TD (Transfer Done) bit of DMA Transfer Status Register
(DMA_TRANS_STATUS) is set to 1. Simultaneously, the DPTD (DMA Pending Transfer Done) bit of Interrupt
Controller DMA Pending Register (INTC_DMA_PEND) is also set to 1. On the other hand, interrupt controller
status registers represent the interrupt sources, which actually generate an interrupt after the masking logic. If the
DMTD (DMA Mask Transfer Done) bit of Interrupt Controller DMA Mask Register (INTC_DMA_MASK) is 0, the
DSTD (DMA Status Transfer Done) bit of the Interrupt Controller DMA Status Register (INTC_DMA_STATUS) is
set to 1 because this interrupt source is not masked. Now, the ARM_IRQ pin of the OneNAND controller is
asserted to 1 and an interrupt is generated by the OneNAND controller. Note that the ARM_IRQ pin is OR-ed
value of all the bits of interrupt controller status registers (INTC_SQC_STATUS, INTC_DMA_STATUS, and
INTC_ONENAND_STATUS) and that this output is asserted if any bit of theses registers is set to 1.
To handle this interrupt in a system, the ISR (interrupt service routine) should perform as follows. The TD
(Transfer Done) bit of DMA Transfer Status Register (DMA_TRANS_STATUS) must be cleared to 0 by writing 1 to
the TDC (Transfer Done Clear) bit of DMA Transfer Command Register (DMA_TRANS_CMD). And then, the
DSTD (DMA Status Transfer Done) bit of the Interrupt Controller DMA Status Register (INTC_DMA_STATUS)
must be cleared to 0 by writing 1 to the DCTD (DMA Clear Transfer Done) bit of the Interrupt Controller DMA
Clear Register (INTC_DMA_CLR).
3.8.4.1 Interrupt Controller DMA Clear Register (INTC_DMA_CLR, W, Address = 0xB060_1004)
INTC_DMA_CLR Bit Description Initial State
- [31:25] Reserved -
DCTD [24]
DMA Clear Transfer Done
When this bit is set to 1, the DSTD (DMA status transfer done)
bit flag of the Interrupt Controller DMA Status Register
(INTC_DMA_STATUS) in the interrupt controller is cleared to 0
0b
- [13:17] Reserved -
DCTE [16]
DMA Clear Transfer Error
When this bit is set to 1, the DPTE (DMA status transfer error)
bit flag of the Interrupt Controller DMA Status Register
(INTC_DMA_STATUS) in the interrupt controller is cleared to 0
0b
- [15:0] Reserved -