Samsung S5PC110, Manual

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S5PC110_UM 1 DRAM CONTROLLER
1-20
1.3.1 PAD MUX FOR ADDRESS CONFIGURATION
PAD Name Config. 1 Config. 2 Config. 3 Config. 4 LPDDR2
Xm1ADDR[0] ADDR_0 ADDR_0 ADDR_0 ADDR_0 CA_0
Xm1ADDR[1] ADDR_1 ADDR_1 ADDR_1 ADDR_1 CA_1
Xm1ADDR[2] ADDR_2 ADDR_2 ADDR_2 ADDR_2 CA_2
Xm1ADDR[3] ADDR_3 ADDR_3 ADDR_3 ADDR_3 CA_3
Xm1ADDR[4] ADDR_4 ADDR_4 ADDR_4 ADDR_4 CA_4
Xm1ADDR[5] ADDR_5 ADDR_5 ADDR_5 ADDR_5 CA_5
Xm1ADDR[6] ADDR_6 ADDR_6 ADDR_6 ADDR_6 CA_6
Xm1ADDR[7] ADDR_7 ADDR_7 ADDR_7 ADDR_7 CA_7
Xm1ADDR[8] ADDR_8 ADDR_8 ADDR_8 ADDR_8 CA_8
Xm1ADDR[9] ADDR_9 ADDR_9 ADDR_9 ADDR_9 CA_9
Xm1ADDR[10] ADDR_10 ADDR_10 ADDR_10 ADDR_10
Xm1ADDR[11] ADDR_11 ADDR_11 ADDR_11 ADDR_11
Xm1ADDR[12] ADDR_12 ADDR_12 ADDR_12 ADDR_12
Xm1ADDR[13] ADDR_13 ADDR_13 ADDR_13 ADDR_13
Xm1ADDR[14] BA_0 BA_0 BA_0 BA_0
Xm1ADDR[15] BA_1 BA_1 BA_1 BA_1
Xm1CSn[1] CS_1 BA_2 BA_2 CS_1
Xm1CSn[0] CS_0 CS_0 CS_0 CS_0 CS_0
Xm1CKE[1] CKE_1 ADDR_14 ADDR_14 CKE_1
Xm1CKE[0] CKE_0 CKE_0 CKE_0 CKE_0 CKE_0
NOTE:
1. Address Config. 1 : The Number of Banks (
MEMCONFIGn.chip_bank
) is set under 4banks and the Number of Row
Address Bits(
MEMCONFIGn.chip_row
) is set under 14bits.
2. Address Config. 2: The Number of Banks (
MEMCONFIGn.chip_bank
) is set under 4banks and the Number of Row
Address Bits(
MEMCONFIGn.chip_row
) is set 15 bits.
3. Address Config. 3: The Number of Banks (
MEMCONFIGn.chip_bank
) is set 8 banks and the Number of Row
Address Bits(
MEMCONFIGn.chip_row
) is set under 14 bits
4. Address Config. 4: The Number of Banks (
MEMCONFIGn.chip_bank
) is set 8 banks and the Number of Row
Address Bits(
MEMCONFIGn.chip_row
) is set 15bits.
5. Address LPDDR2 : The Type of Memory(
MEMCONTROL.mem_type
) is selected LPDDR2.