Samsung S5PC110, Manual

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S5PC110_UM 6 SPDIF TRANSMITTER
6-7
6.4.5 SPDIF OPERATION
Since the bit frequency of SPDIF is 128fs (fs: sampling frequency), divide audio main clock (MCLK) depending on
the frequency of MCLK to make the main clock of SPDIF. MCLK is divided by 2 in case of 256fs, by 3 in case of
384fs and by 4 in case of 512fs.
SPDIF module in S5PC110 changes the audio sample data format to SPDIF. To change the format, SPDIF
module inserts preamble data, channel status data, user data, error check bit and parity bit into the appropriate
time slots. Preamble data are fixed in the module and inserted depending on subframe counter. Channel status
data are set in the SPDCSTAS register and used by one bit per frame. User data always have zero values.
For non-linear PCM data, insert burst-preamble, which consists of Pa, Pb, Pc and Pd, before burst-payload and
zero is padded from the end of burst-payload to the repetition count. Pa(=16'hF872) and Pb(=16'h4E1F) is fixed in
the module and Pc and Pd is set in the register SPDBSTAS. To stuff zero, the end of burst-payload is calculated
from Pd value and repetition count which depends on data type in the preamble Pc is acquired from register
SPDCNT.
Audio data are justified to the LSB. 16-, 20- or 24-bit PCM data and 16-bit stream data are supported. The
unoccupied upper bits of 32-bit word are ignored.
Data are fetched via DMA request. If one of two data buffers is empty, DMA service is requested. Audio data
stored in the data buffers are transformed into SPDIF format and output to the port. For non-linear PCM data,
interrupt is generated after audio data are output up to the value specified in the SPDCNT register. Interrupt sets
the registers such as SPDBSTAS and SPDCNT to new values, if data type of new bitstream is different from the
previous one.