Samsung S5PC110, Manual

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S5PC110_UM 2 1BCAMERA INTERFACE
2-13
2.7.2 CLOCK DOMAIN
Each CAMIF consists of three clock domains. The first clock domain is the system bus clock. The second clock
domain is the camera pixel clock, PCLK. The third clock domain is the internal core clock. The system bus clock
must be faster than the camera pixel clock.
As shown in
Figure 2-11
, CAM_MCLK must be separated from the fixed frequency like PLL clock. If external clock
oscillator is used, CAM_MCLK should be floated. It is not necessary for the three clock domains to synchronize.
Other signals like PCLK should similarly be connected to Schmitt-triggered level shifter.
Figure 2-11 CAMIF Clock Generation
NOTE:
The maximum frequency of core clock is depend on whether user use local path(between display controller) or not.
When it comes to local path between Display Controller, the maximum frequency of core clock is 133MHz(It is recommended
to use MPLL as the source of core clock). For other operation mode except local path, the maximum frequency of core clock is
166MHz(BUS clock should be used).
The maximum frequency of both CAM_MCLK_A and CAM_MCLK_B is 100MHz. And the maximum frequency of both PCLK_A
and PCLK_B is 83MHz.