Samsung S5PC110, Manual

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S5PC110_UM 1 OVERVIEW OF S5PC110
1-4
• 24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA)
• Supports 14x8 key matrix
• 10-channel 12-bit multiplexed ADC
• Configurable GPIOs
• Real time clock, PLL, timer with PWM and watch dog timer
• System timer support for accurate tick time in power down mode (except sleep mode)
• Memory Subsystem
− Asynchronous SRAM/ ROM/ NOR Interface with x8 or x16 data bus
− NAND Interface with x8 data bus
− Muxed/ Demuxed OneNAND Interface with x16 data bus
− LPDDR1 Interface with x16 or x32 data bus (266~400 Mbps/ pin DDR)
− DDR2 interface with x16 or x32 data bus (400 Mbps/ pin DDR)
− LPDDR2 interface (400 Mbps/ pin DDR)
1.3.1 MICROPROCESSOR
The key features of this microprocessor include:
• The ARM CortexTM-A8 processor is the first application processor based on ARMv7 architecture.
• With the ability to scale in speed from 600 MHz to 1 GHz (or more), the ARM CortexTM-A8 processor meets
the requirements of power-optimized mobile devices, which require operation in less than 300mW; and
performance-optimized consumer applications require 2000 Dhrystone MIPS.
• Supports first superscalar processor featuring technology from ARM for enhanced code density and
performance, NEONTM technology for multimedia and signal processing, and Jazelle ® RCT technology for
ahead-of-time and just-in-time compilation of Java and other byte code languages.
• Other features of ARM CortexTM-A8 include:
− Thumb-2 technology for greater performance, energy efficiency, and code density
− NEONTM signal processing extensions
− Jazelle RCT Java-acceleration technology
− TrustZone technology for secure transactions and DRM
− 13-stage main integer pipeline
− 10-stage NEONTM media pipeline
− Integrated L2 Cache using standard compiled RAMs
− Optimized L1 caches for performance and power