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12. Schematic Diagram
12-1
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- NC Point
-Main Chip
Re
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DA
6. Pinning in format io n
Fig 2. PNX4900 ball config urati on diagram
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9
10
11
12
13
14
15
16
17
18
19
A
RFOH
RFOL
GND_RF
VDD_RF
XTAL_SH
LD
XTAL_26
M_2
XTAL_26
M_1
XTAL_SH
LD
GND_VC
ORE
ADDR16
NCS2
NCS0
VDD_VME
M1
VDD_VME
M
VDD_VME
M
ADDR14
DATA6
DATA7
DATA14
B
NO_CON
NECT
GND_RF
GND_RF
VDD_RF
XTAL_SH
LD
XTAL_SH
LD
XTAL_SH
LD
XTAL_SH
LD
GND_VC
ORE
ADDR8
NWE0
NCS1
ADDR15
ADDR22
VDD_VME
M
ADDR21
DATA12
DATA13
DATA5
C
NO_CON
NECT
GND_RF
DATA15
DATA4
D
RFID_P
GND_RF
GND_RF
GND_RF
GND_RF
GND_RF
GND_VC
ORE
ADDR10
ADDR7
NBE0
NRESET_
OUT
ADDR12
ADDR13
VDD_VME
M
ADDR17
DATA11
DATA3
E
RFID_N
GND_RF
GND_RF
GND_RF
GND_RF
GND_RF
GND_VC
ORE
ADDR9
ADDR6
ADDR5
NBE1
NOE
ADDR2
ADDR19
ADDR3
DATA10
DATA2
F
RFIE_P
GND_RF
VDD_RF
GND_RF
ADDR18
ADDR4
DATA9
DATA1
G
RFIE_N
GND_RF
GPIO8
VDD_RF_I
O
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
ADDR11
ADDR1
GND_VSI
M
ADDR20
SIM_RST
DATA0
DATA8
H
GND_RF
GND_RF
GPIO38
GPIO10
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
VDD_VSI
M
GND_GD
GPA
NO_CON
NECT
SIM_DAT
A
SIM_CLK
J
GPIO39
GPIO52
GPIO57 VDD_VIO2
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
FE_CTRL
0
FE_CTRL
1
NO_CON
NECT
NO_CON
NECT
K
KEYIN0
KEYIN1
KEYIN2
VDD_VIO
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
FE_CTRL
2
VDD_RFD
IG
UART0_T
D
XTAL_32K
_2
L
KEYIO0
KEYIO1
KEYIO2
GND_VC
ORE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
FE_CTRL
3
CLK_32K_
OUT
UART0_R
D
XTAL_32K
_1
M
KEYOUT0 KEYOUT1
NTRST
GND_VC
ORE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
VDD_VCO
RE
GND_GD
GPA
PA_RAMP
VBAT_RT
C
AUX_ADC
0
N
KEYOUT2 KEYOUT3
TDI
VDD_VIO
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
GND_VC
ORE
VDD_GPP
M
NO_CON
NECT
NO_CON
NECT
HKSW_D
ET2
P
TDO
TCK
RTCK
VDD_VIO
GND_VBG
VBG
AUXAUD_
IN_L
HKSW_D
ET1
R
SSI_SEL0
TMS
TEST
VDD_VIO
GND_GD
GPA
NO_CON
NECT
AUX_POK
VBAT_SE
NSE
GATE_RE
G
GND_VC
ORE
VBAT_AN
A
VBAT_AN
A
VDD_AUD
IO_DRV
VDD_AUD
IO_DRV
VDD_AUD
IO
AUXAUD_
IN_R
EXTMIC_I
N_N
T
SSI_CLK SSI_SEL2
NRESET
PWM_OU
T1
PWM_OU
T2
PWM_OU
T0
POK_IN
VDD_GPP
M
GND_VBA
T_SNS
VBAT_DC
DC
VBAT_DC
DC
GND_AUD
_DRV
GND_AUD
_DRV
GND_AUD
_DRV
GND_SUB
INTMIC_BI
AS
EXTMIC_I
N_P
U
SSI_DATA SSI_OUT
EXTMIC_
BIAS
INTMIC_IN
_N
V
GPIO41
GPIO2
GPIO6
GPIO7
UART1_T
D
THERM_I
N
UART1_C
TS
POK_OUT
ACC_DET
_IN
VCHG
SWCORE
VCORE
VDD_VPE
RM
PMU_VSI
M
PMU_VME
M
VCM_OUT VCM_OUT GND_AUD
INTMIC_IN
_P
W
GPIO40
GPIO5
GPIO20
GPIO1
UART1_R
D
UART1_R
TS
LDO_EN
ICHGN
ICHGP
GATE_SW SWCORE
PMU_VPE
RM
PMU_VRF
PMU_VAN
A
PMU_VIO
EAR_OUT
_N/R
EAR_OUT
_P/L
HSET_OU
T_N
HSET_OU
T_P