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FPGA35S6046/FPGA35S6101 User’s Manual
6.2.2
R_STATUS
(R
EAD
)
This is a status register for power good (pgood) for the power supplies and serial out from the EEPROM
B0: EEPROM Serial out
B4: 1.2V pgood
B5: 1.8V pgood
B6: 3.3V pgood
6.2.3
R_EEPROM
(R
EAD
/W
RITE
)
This register has the outputs to the EEPROM.
B0: EEPROM Serial Clock
B1: EEPROM Serial Input
B2: EEPROM Chip Select
6.2.4
R_USER_ID
(R
EAD
)
This register shows the status of the User ID Jumpers
B0: User ID 0 Jumper. 0 = Open, 1 = Closed
B1: User ID 1 Jumper. 0 = Open, 1 = Closed
B2: User ID 2 Jumper. 0 = Open, 1 = Closed
B3: User ID 3 Jumper. 0 = Open, 1 = Closed
6.2.5
R_PORT1_IN
(R
EAD
)
This is the input register for the port1. This reads the current value the I/O.
6.2.6
R_PORT1_OUT
(W
RITE
)
This is the output register for the port1. The value to be output, direction must be set to output.
6.2.7
R_PORT1_DIR
(R
EAD
/W
RITE
)
This is
the direction register for port1. Indicates the direction of each pin ‘0’
= input ‘1’ = output
6.2.8
R_PORT2L_IN
(R
EAD
)
This is the input register for the port2 low, port2_[0]
…port2_[15]
. This reads the current value the I/O.
6.2.9
R_PORT2L_OUT
(W
RITE
)
This is the output register for the port2 low, port2_[0]
…port2_[15]
. The value to be output, direction must be set to output.
6.2.10
R_PORT2L_DIR
(R
EAD
/W
RITE
)
This is the direction register for port2 low, port2_[0]
…port2_[15]. Indicates the direction of each pin ‘0’ = input ‘1’ = output
6.2.11
R_PORT2H_IN
(R
EAD
)
This is the input register for the port2 high, port2_[16]
…port2_[19]
. This reads the current value the I/O.
6.2.12
R_PORT2H_OUT
(W
RITE
)
This is the output register for the port2 high, port2_[16]
…port2_[19]
. The value to be output, direction must be set to output.
