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49
DMx820 User’s Manual
Field
Description
WRITE_REQ
Current Write Request Status.
’0’ = Not ready to receive data
’1’ = Ready to receive data.
READ_REQ
Current Read Request Status.
’0’ = Not ready to send data
’1’ = Ready to send data.
ENA
FIFO Enable.
’0’ = FIFO is disabled and cleared
’1’ = FIFO is enabled.
FIFOn_RW_PORT
This register provides the PCI bus access to the FIFO. Reads from this register return the current data that is available at the output of the
FIFO, and can be programmed to clock the next data out of the FIFO. Writes to this register can be programmed to write data into the FIFO.
Accesses to this register must be word (16-bit) or larger.
15
0
DATA[15:0]
RW,+0
Field
Description
DATA
The read or write data to the FIFO.
6.3.5
P
ROGRAMMABLE
C
LOCK N
There are four programmable clocks on the DMx820HR. They can be cascaded. The Programmable Clocks use a master clock and divide it
down by an integer,
An interrupt is generated at every positive edge of the clock output.
PROGCLKn_ID
ID register to identify a Programmable Clock Block.
15
0
ID_Register
R
Field
Description
ID_Register15:0]
Value of 0x1000 indicates Programmable Clock
PROGCLKn_MODE
Selects the mode that the Programmable Clock.
15
2
1 0
Reserved
MODE
RW,+0
RW,+00