rtd DM35820HR, User Manual, Page: 74 / 82

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2 Abort. Writing 1 causes the channel to abort
the current transfer. The DMA Channel 0
Enable bit must be cleared (DMACSR0[0]=0).
Sets the DMA Channel 0 Done bit
(DMACSR0[4]=1) when the abort is complete.
Yes Yes/
Set 0h x
3 Clear Interrupt. Writing 1 clears DMA
Channel 0 interrupts.
Yes Yes/
Clr 0h x
4 Done. Reading 1 indicates the transfer is
complete. The transfer may be complete
either because the DMA transfer finished
successfully, or that the DMA transfer was
aborted when software set the Abort bit
(DMACSR0[2]=1). Reading 0 indicates the
Channel transfer is not complete.
Yes No 0h x
7:5
Reserved.
Yes No 000b 000b
DMAARB
DMA Arbitration
Bit Description Read Write Value
after
Reset
Value
to Use
18:0 Reserved. Yes (Do not
Modify) 0 0
20:19
DMA Channel Priority. Writing 00b indicates a
rotational priority scheme. Writing 01b
indicates Channel 0 has priority. Writing 10b
indicates Channel 1 has priority. Value of 11b
is
reserved .
Yes Yes 00b 00b
31:21 Reserved. Yes (Do not
Modify) 0000
0000
001b 0000
0011
001b
DMATHR
DMA Threshold
Bit Description Read Write Value
after
Reset
Value
to Use
3:0 DMA Channel 0 PCI-to-Local Almost Full (C0PLAF).
Number of full (Lword x 2) entries (plus 1, times 2) in
the FIFO before requesting the Local Bus for writes.
Nybble values 0h through Eh may be used. (Refer to
Table 17.)
(15 - C0PLAF) > C0LPAE.
Yes Yes 0h x
7:4 DMA Channel 0 Local-to-PCI Almost Empty
(C0LPAE).
Number of empty (Lword x 2) entries (plus
1, times 2) in the FIFO before requesting the Local Bus
for reads. Nybble values 0h through Eh may be used.
(Refer to Table 17.)
(15 - C0PLAF) > C0LPAE.
Yes Yes 0h x
11:8 DMA Channel 0 Local-to-PCI Almost Full
(C0LPAF).
Number of full (Lword x 2) entries
(plus 1, times 2) in the FIFO before requesting
the PCI Bus for writes. Nybble values 0h
through Eh may be used. (Refer to
Table 17
.)
Yes Yes 0h x