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59
DMx820 User’s Manual
6.3.8
Q
UAD
P
ULSE
W
IDTH
M
ODULATOR N
The Pulse Width Modulator block provides four PWM outputs. Each output consists of a non-inverted and inverted signal. These signals are
available on select pins as peripheral outputs. The period and width of the output is set with 16 bit resolution.
Figure 13: PWM Output
All of the PWM outputs have the same period. The pulse width of each of the four outputs is individually adjustable.
The PWM can use separate clocks for width and period. The width clock is used to decrement the counter. When the counter reaches zero, it
will wait for the next period clock to re-load the counter with the period value.
In a typical PWM implementation, the same clock is used for width and period. By using separate clocks, a high resolution can be achieved
with low duty cycle outputs. For example, if a 1 MHz clock is used for the period clock and the PERIOD register is set to its maximum value,
and a 10 MHz clock is used for the width clock, the duty cycle range is 0% to 10%, with a full 16 bit resolution across that range.
Note that if the PERIOD register is set to its maximum value, a duty cycle of 100% cannot be achieved.
An interrupt is generated at the beginning of every period.
The width register is checked at the beginning of every period. If the width register is modified in the middle of a period, the output will not be
affected until the next period.
PWMn_ID
ID register to identify this block.
15
0
ID_Register
R
Field
Description
ID_Register15:0]
Value of 0x0003 indicates Pulse Width Modulator
PWMn_MODE
This register is used to enable and disable the Pulse Width Modulator. When disabled, all non-inverted outputs are low, and all inverted
outputs are high, and interrupts are not generated.
15
1
0
Reserved
ENA
R,+0
RW,+0
Output -
Interrupt
(WIDTH)/(Width_Clock_Freq)
(1)/( Width_Clock_Freq)
Period_Clock Edge
