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48
DMx820 User’s Manual
Field
Description
7 82C54 TC B2
6 82C54 TC B1
5 82C54 TC B0
4 82C54 TC A2
3 82C54 TC A1
2 82C54 TC A0
1 Reserved
0 25 MHz
FIFOn_IN_DATA_DREQ
This register selects the FIFO data input and PLX DMA Request source. For the “Write Request” and “Read Request” signals, in
ternal buffers
are monitored to signal when data can be sent into, and read from the FIFO. The “Write Request” is asserted when th
ere are at least 256
words of space available in the FIFO, and negated when there are
less than 128 words available. The “Read Request” is asserted when at
least 256 words of data is in the FIFO, and negated when there is less than 128 words of data. Using these signals guarantees a burst of at
least 128 words, which provides for efficient communication over the PCI bus, and robustly guards against over-run and under-run conditions.
However, it does not allow for the FIFO to be completely filled of emptied.
The “Not Full” and “Not Empty” request source should only be used if the amount of data in the FIFO is known, or to finish fi
lling/emptying the
FIFO. The DMA engine on the PLX PCI9056 will complete an additional double-word transfer after the request is negated. Therefore, using
the “Not Full” and “Not Empty” request source will generally result in an over
-run/under-run condition whenever the signal is negated.
The DREQ signals are in an undefined state when the FIFO is disabled. The DMA engine should only be enabled after the FIFO is enabled
(FIFOn_CON_STAT[ENA]).
15
10
9
8
7
2
1
0
Reserved
DREQ_SRC[1:0]
Reserved
IN_DATA[1:0]
R,+0
RW,+0
R,+0
RW,+0
Field
Description
DREQ_SRC[1:0]
Selects the source for the DREQn signal to the PLX chip.
Value definitions are:
3 = Not Full
2 = Write Request
1 = Not Empty
0 = Read Request
IN_DATA[1:0]
Selects the FIFO Input Data.
Value definitions for FIFO0 are:
3 = FIFO0 Output
2 = Port 2
1 = Port 0
0 = PCI Data
Value definitions for FIFO1 are:
3 = Incremental Encoder 1 Channel B Value
2 = Incremental Encoder 1 Channel A Value
1 = Port 1
0 = PCI Data
FIFOn_CON_STAT
This register is used to enable the FIFO. When the FIFO is disabled, it is internally reset, and all data is flushed from it.
This register also is used to read the current status of the “Write Request” and “Read Request” signals that are used for DMA
Requests. For
these signals, internal buffers are monitored to signal when data can be sent into, and read from the FIFO. The “Write Request” is asserted
when there are at least 256 words of space available in the FIFO, and negated when there are
less than 128 words available. The “Read
Request” is asserted when at least 256 words of data is in the FIFO, and negated when there is
less than 128 words of data. Using these
signals guarantees a burst of at least 128 words, which provides for efficient communication over the PCI bus, and robustly guards against
over-run and under-run conditions. However, it does not allow for the FIFO to be completely filled of emptied.
15 10
9
8
7 1
0
Reserved
WRITE_REQ
READ_REQ
Reserved
ENA
R,+0
R,+x
R,+0
R,+0
RW,+0