RTD Embedded Technologies, Inc.
|
www.rtd.com
26
DMx820 User’s Manual
Description
Max Data Rate
One FIFO in use, burst capture only
25 MHz
One FIFO in use, burst output only
25 MHz
One FIFO in use, continuous capture or output
12.5 MHz
Two FIFOs in use, continuous capture/output
12.5 MHz +
6.25 MHz
Two FIFOs in use, continuous capture/output,
non-uniform sampling
11 MHz +
11 MHz
Board Interrupts
There are three levels of interrupt sources for this board: the interrupt sources generated in the PLX chip, the interrupt sources generated by
the modules in the Control Block, and the interrupt sources within the modules. Each level must be enabled in the previous level. Figure 10
shows a block diagram of the interrupt sources. Note that there are some other sources in the PLX bridge chip; consult the datasheet for more
details.
INTA#
D
Q
DMAMODE0[10]
DMA Channel 0 Done
D
Q
DMAPR0[2]
DMA Channel 0 TC
D
Q
INTCSR[18],
DMAMODE0[17]
D
Q
DMAMODE1[10]
DMA Channel 1 Done
D
Q
DMAPR1[2]
DMA Channel 1 TC
D
Q
INTCSR[19],
DMAMODE1[17]
D
Q
CNTRL[20]
D
Q
INT_ENA[16:0]
INT_STAT[16:0]
D
Q
x_ENA[]
x_STAT[]
...
PLX
Control Block
Modules
Figure 10: Interrupt Diagram
Advanced Triggering Examples
The modules on the DMx820HR can be combined to generate a broad range of complex sampling scenarios. The following example shows
how to use the Advanced Interrupt and 4 counters to capture N words before and M words after an event. Programmable Clock 0 is the
sample clock, and is used to clock data into the FIFO. It is started after all of the other Programmable clocks are initialized. As soon as it
starts, Programmable Clock 1 starts counting samples to be captured before the triggering event. This is also known as “pre
-
fill.”
When it
expires, it starts Programmable Clock 2, which removes samples from the FIFO at the same rate that they are stored, keeping a constant
number of samples in the FIFO. When the triggering event happens, Programmable Clock 2 is stopped, and the FIFO begins to fill. Also, the
triggering event starts Programmable Clock 3, which counts the number of samples to be captured after the triggering event. When
Programmable Clock 3 expires, it stops Programmable Clock 0, and data collection ends. The triggering event can also generate an interrupt
that changes the FIFO output to PCI Read, and start DMA transfers. This allows the data to be moved to system memory before data
collection has ended.
1)
AdvInt0
a)
Set to event desired
b)
During the Interrupt Service Rout
ine…
i)
Change FIFO output clock to PCI Read
ii)
Start DMA transfers
2)
Prog Clock 0 - Sample Input Clock
a)
Period = sample period
b)
Master Clock = any
