rtd DM35425, User Manual

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RTD Embedded Technologies, Inc.
| www.rtd.com 49 DM35425HR User’s Manual
6.5.16 DIO_INPUT (R
EAD
O
NLY
)
This register provides the current value on the Digital I/O lines regardless of pin direction. The bits in the register correspond with the Digital
I/O pins as follows:
This is the same value that is written to the DMA INPUT FIFO.
When P_BUS_EN is enabled and the P_BUS_CLK pin direction is set to high this Register and DMA INPUT FIFO will only be updated when
receives a high clock pulse and P_BUS_VALID is high.
Bit CN4 Pin
Number
Signal Name
P_BUS_EN = 0 P_BUS_EN = 1
31 24 DIO31 P_BUS_CLK
30 26 DIO30 P_BUS_READY
29 28 DIO29 P_BUS_VALID
28 30 DIO28 P_BUS_DATA28
27 32 DIO27 P_BUS_DATA27
26 34 DIO26 P_BUS_DATA26
25 36 DIO25 P_BUS_DATA25
24 38 DIO24 P_BUS_DATA24
23 23 DIO23 P_BUS_DATA23
22 25 DIO22 P_BUS_DATA22
21 27 DIO21 P_BUS_DATA21
20 29 DIO20 P_BUS_DATA20
19 31 DIO19 P_BUS_DATA19
18 33 DIO18 P_BUS_DATA18
17 35 DIO17 P_BUS_DATA17
16 37 DIO16 P_BUS_DATA16
Bit CN3 Pin
Number
Signal Name
P_BUS_EN = 0 P_BUS_EN = 1
15 24 DIO15 P_BUS_DATA15
14 26 DIO14 P_BUS_DATA14
13 28 DIO13 P_BUS_DATA13
12 30 DIO12 P_BUS_DATA12
11 32 DIO11 P_BUS_DATA11
10 34 DIO10 P_BUS_DATA10
9 36 DIO9 P_BUS_DATA9
8 38 DIO8 P_BUS_DATA8
7 23 DIO7 P_BUS_DATA7
6 25 DIO6 P_BUS_DATA6
5 27 DIO5 P_BUS_DATA5
4 29 DIO4 P_BUS_DATA4
3 31 DIO3 P_BUS_DATA3
2 33 DIO2 P_BUS_DATA2
1 35 DIO1 P_BUS_DATA1
0 37 DIO0 P_BUS_DATA0
6.5.17 DIO_OUTPUT (R
EAD
/W
RITE
)
The last value sent to the Digital I/O Output.
If the c urrent Mode is “Reset” or the associated DMA engine is set to “Clear”, a write to this register will immediately update the D igital I/O
Output. Bit assignments are the same as above.
When P_BUS_EN is enabled
B[31:29]: Reserved
B[28:0]: P_BUS_DATA
6.5.18 DIO_DIRECTION (R
EAD
/W
RITE
)
The last value sent to the Digital I/O Direction.
If the current Mode is “Reset” or the associated DMA engine is set to “Clear”, a write to this register will immediately upda te the Digital I/O
Direction. Bit assignments are the same as above.
Selects the direction of the I/O bit. 0=input, 1=output.
All pins default to inputs at power-up.
When P_BUS_EN is enabled
B[31]: P_BUS_CLK: When set high, data in the Digital I/O DMA OUTPUT FIFO and high clock pulse (50ns) will be sent every
Digital I/O pacer clock. When set low, DIO_INPUT Register and DMA INPUT FIFO will be updated every high
clock pulse received.
B[30]: P_BUS_READY: When set high, this will output high ready signal once the Digital I/O DMA INPUT FIFO is setup and started.
When using the module to send data, set this bit low to receive the ready signal.